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RISC-V: Zfinx-related fixes (1) #64

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RISC-V: Zfinx-related fixes (1) #64

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a4lg
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@a4lg a4lg commented Sep 27, 2022

@a4lg a4lg changed the base branch from master to riscv-common-regpair September 27, 2022 13:54
@a4lg a4lg force-pushed the riscv-float-combined-1 branch from d77f587 to 62a90fe Compare September 27, 2022 14:07
@a4lg a4lg force-pushed the riscv-common-regpair branch 2 times, most recently from 60bedc4 to e486b23 Compare September 27, 2022 14:10
@a4lg a4lg force-pushed the riscv-float-combined-1 branch 3 times, most recently from c83a5db to 2f0633c Compare September 28, 2022 07:21
@a4lg a4lg force-pushed the riscv-common-regpair branch from 26681d1 to 6772709 Compare September 30, 2022 04:26
@a4lg a4lg force-pushed the riscv-float-combined-1 branch from 2f0633c to 39a4bb6 Compare September 30, 2022 04:26
a4lg added 3 commits September 30, 2022 14:38
@a4lg
RISC-V: Implement extension variants
86a57e9 
TODO

gas/ChangeLog:

	* config/tc-riscv.c (riscv_ip): Add empty INSN_HAS_EXT_VARS
	handling.

include/ChangeLog:

	* opcode/riscv.h (INSN_HAS_EXT_VARS): New.
@a4lg
RISC-V: Reorganize and enhance 'Zfinx' tests
5c1dd6d 
This commit adds certain test cases for 'Zfinx'/'Zdinx'/'Zqinx' extensions
and reorganizes them, fixing coding style while improving coverage.
This is partially based on jiawei's 'Zhinx' testcases.

gas/ChangeLog:

	* testsuite/gas/riscv/zfinx.s: Use different registers for
	better encode space testing.  Make indentation consistent.
	Add tests for instruction with rounding mode.  Change march
	to minimum required extensions.  Remove source line.
	* testsuite/gas/riscv/zfinx.d: Likewise.
	* testsuite/gas/riscv/zdinx.s: Likewise.
	* testsuite/gas/riscv/zdinx.d: Likewise.
	* testsuite/gas/riscv/zqinx.s: Likewise.
	Also use even-numbered registers to use valid register pairs.
	* testsuite/gas/riscv/zqinx.d: Likewise.

Signed-off-by: Tsukasa OI <[email protected]>
Signed-off-by: jiawei <[email protected]>
@a4lg
RISC-V: Relax "fmv.[sdq]" requirements
0415635 
This commit relaxes requirements to "fmv.s" instructions from 'F' to ('F'
or 'Zfinx').  The same applies to "fmv.d" and "fmv.q".  Note that 'Zhinx'
extension already contains "fmv.h" instruction (as well as 'Zfh').

gas/ChangeLog:

	* testsuite/gas/riscv/zfinx.s: Add "fmv.s" instruction.
	* testsuite/gas/riscv/zfinx.d: Likewise.
	* testsuite/gas/riscv/zdinx.s: Add "fmv.d" instruction.
	* testsuite/gas/riscv/zdinx.d: Likewise.
	* testsuite/gas/riscv/zqinx.d: Add "fmv.q" instruction.
	* testsuite/gas/riscv/zqinx.s: Likewise.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Relax requirements to "fmv.[sdq]"
	instructions to support those in 'Zfinx'/'Zdinx'/'Zqinx'.
@a4lg a4lg force-pushed the riscv-common-regpair branch from 6772709 to 9bdd540 Compare September 30, 2022 14:55
@a4lg a4lg force-pushed the riscv-float-combined-1 branch from 39a4bb6 to 0415635 Compare September 30, 2022 14:55
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a4lg commented Sep 30, 2022

Closed beacuse upstreamed as commits 38cb335 and cfc0ffd.

@a4lg a4lg closed this Sep 30, 2022
@a4lg a4lg added the enhancement New feature or request label Oct 1, 2022
@a4lg a4lg deleted the riscv-float-combined-1 branch October 29, 2022 06:02
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