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(old branch) RISC-V: Zfinx-related fixes (1) #63

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(old branch) RISC-V: Zfinx-related fixes (1) #63

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@a4lg a4lg commented Sep 27, 2022 •
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a4lg added 3 commits September 27, 2022 09:00
@a4lg
RISC-V: Implement common register pair framework
bab0732 
This commit implements common framework for register pairs or quad-register
pairs (using GPRs).  This is particularly useful on following extensions:

-   Zdinx
-   Zqinx (not ratified yet)
-   Zpsfoperand (a part of 'P' extension proposal)

New operand type format is shown below:

1.  'l' (stands for "length")
2.  '1' for  32-bit data (or less), (RV32: 1 register,  RV64: 1 register)
    '2' for  64-bit data            (RV32: 2 registers, RV64: 1 register)
    '4' for 128-bit data            (RV32: 4 registers, RV64: 2 registers)
3.  'd' for RD
    's' for RS1
    't' for RS2
    'r' for RS3
    'u' for RS1 and RS2 (RS1 == RS2)

gas/ChangeLog:

	* config/tc-riscv.c (riscv_ip): Add handling for "l[124][dstru]".
	(validate_riscv_insn): Likewise.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Add handling for "l[124][dstru]".
@a4lg
RISC-V: Reorganize and enhance Zfinx tests
8a842f1 
This commit adds certain test cases for Zfinx/Zdinx/Zqinx extensions
and reorganizes them, fixing coding style while improving coverage.
This is partially based on jiawei's Zhinx testcases.

gas/ChangeLog:

	* testsuite/gas/riscv/zfinx.s: Use different registers for
	better encode space testing / make indentation consistent /
	add tests for instruction with rounding mode.
	* testsuite/gas/riscv/zfinx.d: Likewise.
	* testsuite/gas/riscv/zdinx.s: Use different registers for
	better encode space testing / make indentation consistent /
	add tests for instruction with rounding mode.
	* testsuite/gas/riscv/zdinx.d: Likewise.
	* testsuite/gas/riscv/zqinx.s: Use different registers for
	better encode space testing / make indentation consistent /
	add tests for instruction with rounding mode / use even-numbered
	registers to use valid register pairs.
	* testsuite/gas/riscv/zqinx.d: Likewise.

Signed-off-by: Tsukasa OI <[email protected]>
Signed-off-by: jiawei <[email protected]>
@a4lg
RISC-V: Relax fmv.[sdq] requirements
d77f587 
This commit relaxes requirements to fmv.s instructions from 'F' to ('F'
or 'Zfinx').  The same applies to fmv.d and fmv.q.  Note that 'Zhinx'
extension already contains fmv.h instruction (as well as 'Zfh').

gas/ChangeLog:

	* testsuite/gas/riscv/zfinx.s: Add fmv.s instruction.
	* testsuite/gas/riscv/zfinx.d: Likewise.
	* testsuite/gas/riscv/zdinx.s: Add fmv.d instruction.
	* testsuite/gas/riscv/zdinx.d: Likewise.
	* testsuite/gas/riscv/zqinx.d: Add fmv.q instruction.
	* testsuite/gas/riscv/zqinx.s: Likewise.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Relax requirements to
	fmv.[sdq] instructions to support those in Zfinx/Zdinx/Zqinx.
@a4lg a4lg closed this Sep 27, 2022
@a4lg a4lg deleted the riscv-float-combined-min branch September 27, 2022 13:50
@a4lg a4lg changed the title RISC-V: Zfinx-related fixes (1) (old branch) RISC-V: Zfinx-related fixes (1) Oct 1, 2022
@a4lg a4lg added the invalid This doesn't seem right label Oct 1, 2022
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