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RISC-V: Fix CSR accessibility and implications #44

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RISC-V: Fix CSR accessibility and implications #44

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09d1039
RISC-V: Fix vector CSR implication
a4lg Sep 5, 2022
4c60a55
RISC-V: Imply 'Zicsr' from 'Zkr'
a4lg Sep 5, 2022
4140cf7
RISC-V: Imply 'Zicsr' from some privileged extensions
a4lg Sep 5, 2022
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6 changes: 6 additions & 0 deletions bfd/elfxx-riscv.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1047,6 +1047,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"g", "d", check_implicit_always},
{"g", "zicsr", check_implicit_always},
{"g", "zifencei", check_implicit_always},
{"h", "zicsr", check_implicit_always},
{"q", "d", check_implicit_always},
{"v", "d", check_implicit_always},
{"v", "zve64d", check_implicit_always},
Expand All @@ -1062,6 +1063,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"zve64x", "zve32x", check_implicit_always},
{"zve64x", "zvl64b", check_implicit_always},
{"zve32x", "zvl32b", check_implicit_always},
{"zve32x", "zicsr", check_implicit_always},
{"zvl65536b", "zvl32768b", check_implicit_always},
{"zvl32768b", "zvl16384b", check_implicit_always},
{"zvl16384b", "zvl8192b", check_implicit_always},
Expand Down Expand Up @@ -1091,11 +1093,15 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"zkn", "zkne", check_implicit_always},
{"zkn", "zknd", check_implicit_always},
{"zkn", "zknh", check_implicit_always},
{"zkr", "zicsr", check_implicit_always},
{"zks", "zbkb", check_implicit_always},
{"zks", "zbkc", check_implicit_always},
{"zks", "zbkx", check_implicit_always},
{"zks", "zksed", check_implicit_always},
{"zks", "zksh", check_implicit_always},
{"smstateen", "zicsr", check_implicit_always},
{"sscofpmf", "zicsr", check_implicit_always},
{"sstc", "zicsr", check_implicit_always},
{NULL, NULL, NULL}
};

Expand Down
6 changes: 6 additions & 0 deletions gas/testsuite/gas/riscv/march-imply-h.d
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@@ -0,0 +1,6 @@
#as: -march=rv32ih -march-attr -misa-spec=20191213 -mpriv-spec=1.12
#readelf: -A
#source: empty.s
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p1_h1p0_zicsr2p0"
21 changes: 21 additions & 0 deletions gas/testsuite/gas/riscv/vector-csrs-zve32f.d
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#as: -march=rv32i_zve32f -mcsr-check
#source: vector-csrs.s
#objdump: -d

.*:[ ]+file format .*


Disassembly of section .text:

0+000 <target>:
[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart
[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero
[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat
[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1
[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm
[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3
[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr
[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7
[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl
[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype
[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb
21 changes: 21 additions & 0 deletions gas/testsuite/gas/riscv/vector-csrs-zve32x.d
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@@ -0,0 +1,21 @@
#as: -march=rv32i_zve32x -mcsr-check
#source: vector-csrs.s
#objdump: -d

.*:[ ]+file format .*


Disassembly of section .text:

0+000 <target>:
[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart
[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero
[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat
[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1
[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm
[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3
[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr
[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7
[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl
[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype
[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb
21 changes: 21 additions & 0 deletions gas/testsuite/gas/riscv/vector-csrs-zve64d.d
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#as: -march=rv32i_zve64d -mcsr-check
#source: vector-csrs.s
#objdump: -d

.*:[ ]+file format .*


Disassembly of section .text:

0+000 <target>:
[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart
[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero
[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat
[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1
[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm
[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3
[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr
[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7
[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl
[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype
[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb
21 changes: 21 additions & 0 deletions gas/testsuite/gas/riscv/vector-csrs-zve64f.d
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#as: -march=rv32i_zve64f -mcsr-check
#source: vector-csrs.s
#objdump: -d

.*:[ ]+file format .*


Disassembly of section .text:

0+000 <target>:
[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart
[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero
[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat
[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1
[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm
[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3
[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr
[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7
[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl
[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype
[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb
21 changes: 21 additions & 0 deletions gas/testsuite/gas/riscv/vector-csrs-zve64x.d
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@@ -0,0 +1,21 @@
#as: -march=rv32i_zve64x -mcsr-check
#source: vector-csrs.s
#objdump: -d

.*:[ ]+file format .*


Disassembly of section .text:

0+000 <target>:
[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart
[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero
[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat
[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1
[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm
[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3
[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr
[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7
[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl
[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype
[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb
20 changes: 20 additions & 0 deletions gas/testsuite/gas/riscv/vector-csrs.d
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@@ -0,0 +1,20 @@
#as: -march=rv32iv -mcsr-check
#objdump: -d

.*:[ ]+file format .*


Disassembly of section .text:

0+000 <target>:
[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart
[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero
[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat
[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1
[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm
[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3
[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr
[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7
[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl
[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype
[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb
12 changes: 12 additions & 0 deletions gas/testsuite/gas/riscv/vector-csrs.s
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@@ -0,0 +1,12 @@
target:
csrr a0, vstart
csrw vstart, zero
csrr a0, vxsat
csrwi vxsat, 1
csrr a0, vxrm
csrwi vxrm, 3
csrr a0, vcsr
csrwi vcsr, 7
csrr a0, vl
csrr a0, vtype
csrr a0, vlenb
10 changes: 10 additions & 0 deletions gas/testsuite/gas/riscv/zkr.d
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@@ -0,0 +1,10 @@
#as: -march=rv32i_zkr -mcsr-check
#objdump: -d

.*:[ ]+file format .*


Disassembly of section .text:

0+000 <target>:
[ ]+[0-9a-f]+:[ ]+01502573[ ]+csrr[ ]+a0,seed
2 changes: 2 additions & 0 deletions gas/testsuite/gas/riscv/zkr.s
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@@ -0,0 +1,2 @@
target:
csrr a0, seed