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Disassembler: Fix address printer #30

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Disassembler: Fix address printer #30

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43c1afb
RISC-V: Add address printer tests with ADDIW
a4lg Aug 26, 2022
d2365c9
RISC-V: Fix JALR target address computation
a4lg Aug 26, 2022
d98eb0c
RISC-V: Fix RV32 disassembler address computation
a4lg Aug 26, 2022
b6e5117
RISC-V: Print highest address on the disassembler
a4lg Aug 26, 2022
154e28c
RISC-V: Print top GP-relative addresses on the disassembler
a4lg Aug 26, 2022
2a1b867
RISC-V: Clarify that `wide' is only used for ADDIW
a4lg Aug 26, 2022
c88d112
RISC-V: Make `is_addiw' parameter bool
a4lg Aug 26, 2022
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18 changes: 18 additions & 0 deletions gas/testsuite/gas/riscv/dis-addr-addiw-a.d
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#as: -march=rv64ic
#source: dis-addr-addiw.s
#objdump: -d --adjust-vma=0xffffffe0

.*: file format elf64-(little|big)riscv


Disassembly of section .text:

0+ffffffe0 <_start>:
[ ]+ffffffe0:[ ]+00000297[ ]+auipc[ ]+t0,0x0
[ ]+ffffffe4:[ ]+0182831b[ ]+addiw[ ]+t1,t0,24 # fffffffffffffff8 <addr_rv64_addiw_0a>
[ ]+ffffffe8:[ ]+00000397[ ]+auipc[ ]+t2,0x0
[ ]+ffffffec:[ ]+01c38e1b[ ]+addiw[ ]+t3,t2,28 # 4 <addr_rv64_addiw_0b>
[ ]+fffffff0:[ ]+00000e97[ ]+auipc[ ]+t4,0x0
[ ]+fffffff4:[ ]+2eb1[ ]+addiw[ ]+t4,t4,12 # fffffffffffffffc <addr_rv64_c_addiw_0a>
[ ]+fffffff6:[ ]+00000f17[ ]+auipc[ ]+t5,0x0
[ ]+fffffffa:[ ]+2f49[ ]+addiw[ ]+t5,t5,18 # 8 <addr_rv64_c_addiw_0b>
18 changes: 18 additions & 0 deletions gas/testsuite/gas/riscv/dis-addr-addiw-b.d
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#as: -march=rv64ic
#source: dis-addr-addiw.s
#objdump: -d --adjust-vma=0x7fffffe0

.*: file format elf64-(little|big)riscv


Disassembly of section .text:

0+7fffffe0 <_start>:
[ ]+7fffffe0:[ ]+00000297[ ]+auipc[ ]+t0,0x0
[ ]+7fffffe4:[ ]+0182831b[ ]+addiw[ ]+t1,t0,24 # 7ffffff8 <addr_rv64_addiw_1a>
[ ]+7fffffe8:[ ]+00000397[ ]+auipc[ ]+t2,0x0
[ ]+7fffffec:[ ]+01c38e1b[ ]+addiw[ ]+t3,t2,28 # ffffffff80000004 <addr_rv64_addiw_1b>
[ ]+7ffffff0:[ ]+00000e97[ ]+auipc[ ]+t4,0x0
[ ]+7ffffff4:[ ]+2eb1[ ]+addiw[ ]+t4,t4,12 # 7ffffffc <addr_rv64_c_addiw_1a>
[ ]+7ffffff6:[ ]+00000f17[ ]+auipc[ ]+t5,0x0
[ ]+7ffffffa:[ ]+2f49[ ]+addiw[ ]+t5,t5,18 # ffffffff80000008 <addr_rv64_c_addiw_1b>
28 changes: 28 additions & 0 deletions gas/testsuite/gas/riscv/dis-addr-addiw.s
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.set addr_rv64_addiw_0a, 0xfffffffffffffff8 # 0xffffffe0 + 0x18 (sext:32->64)
.set addr_rv64_c_addiw_0a, 0xfffffffffffffffc # 0xfffffff0 + 0x0c (sext:32->64)
.set addr_rv64_addiw_0b, 0x00000004 # 0xffffffe8 + 0x1c
.set addr_rv64_c_addiw_0b, 0x00000008 # 0xfffffff6 + 0x12
.set addr_rv64_addiw_1a, 0x7ffffff8 # 0x7fffffe0 + 0x18
.set addr_rv64_c_addiw_1a, 0x7ffffffc # 0x7ffffff0 + 0x0c
.set addr_rv64_addiw_1b, 0xffffffff80000004 # 0x7fffffe8 + 0x1c (sext:32->64)
.set addr_rv64_c_addiw_1b, 0xffffffff80000008 # 0x7ffffff6 + 0x12 (sext:32->64)

.text
.global _start
_start:
.option push
.option arch, -c
# _start + 0x00
auipc t0, 0
addiw t1, t0, 0x18
# _start + 0x08
auipc t2, 0
addiw t3, t2, 0x1c

.option pop
# _start + 0x10
auipc t4, 0
c.addiw t4, 0x0c
# _start + 0x16
auipc t5, 0
c.addiw t5, 0x12
30 changes: 30 additions & 0 deletions gas/testsuite/gas/riscv/dis-addr-overflow-32.d
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#as: -march=rv32ic
#source: dis-addr-overflow.s
#objdump: -d

.*: file format elf32-(little|big)riscv


Disassembly of section .text:

0+000 <target>:
[ ]+[0-9a-f]+:[ ]+fffff2b7[ ]+lui[ ]+t0,0xfffff
[ ]+[0-9a-f]+:[ ]+ffc2a903[ ]+lw[ ]+s2,-4\(t0\) # ffffeffc <addr_load>
[ ]+[0-9a-f]+:[ ]+ffffe337[ ]+lui[ ]+t1,0xffffe
[ ]+[0-9a-f]+:[ ]+ff332c23[ ]+sw[ ]+s3,-8\(t1\) # ffffdff8 <addr_store>
[ ]+[0-9a-f]+:[ ]+ffffd3b7[ ]+lui[ ]+t2,0xffffd
[ ]+[0-9a-f]+:[ ]+000380e7[ ]+jalr[ ]+t2 # ffffd000 <addr_jalr_1>
[ ]+[0-9a-f]+:[ ]+ffffce37[ ]+lui[ ]+t3,0xffffc
[ ]+[0-9a-f]+:[ ]+ff4e00e7[ ]+jalr[ ]+-12\(t3\) # ffffbff4 <addr_jalr_2>
[ ]+[0-9a-f]+:[ ]+ffffbeb7[ ]+lui[ ]+t4,0xffffb
[ ]+[0-9a-f]+:[ ]+000e8a67[ ]+jalr[ ]+s4,t4 # ffffb000 <addr_jalr_3>
[ ]+[0-9a-f]+:[ ]+ffffaf37[ ]+lui[ ]+t5,0xffffa
[ ]+[0-9a-f]+:[ ]+ff0f0a93[ ]+addi[ ]+s5,t5,-16 # ffff9ff0 <addr_loadaddr>
[ ]+[0-9a-f]+:[ ]+ffff9fb7[ ]+lui[ ]+t6,0xffff9
[ ]+[0-9a-f]+:[ ]+1fb1[ ]+addi[ ]+t6,t6,-20 # ffff8fec <addr_loadaddr_c>
[ ]+[0-9a-f]+:[ ]+4001a283[ ]+lw[ ]+t0,1024\(gp\) # 600 <addr_rel_gp_pos>
[ ]+[0-9a-f]+:[ ]+c001a303[ ]+lw[ ]+t1,-1024\(gp\) # fffffe00 <addr_rel_gp_neg>
[ ]+[0-9a-f]+:[ ]+10002383[ ]+lw[ ]+t2,256\(zero\) # 100 <addr_rel_zero_pos>
[ ]+[0-9a-f]+:[ ]+80002e03[ ]+lw[ ]+t3,-2048\(zero\) # fffff800 <addr_rel_zero_neg>
[ ]+[0-9a-f]+:[ ]+10400ee7[ ]+jalr[ ]+t4,260\(zero\) # 104 <addr_jalr_rel_zero_pos>
[ ]+[0-9a-f]+:[ ]+80400f67[ ]+jalr[ ]+t5,-2044\(zero\) # fffff804 <addr_jalr_rel_zero_neg>
34 changes: 34 additions & 0 deletions gas/testsuite/gas/riscv/dis-addr-overflow-64.d
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#as: -march=rv64ic -defsym rv64=1
#source: dis-addr-overflow.s
#objdump: -d

.*: file format elf64-(little|big)riscv


Disassembly of section .text:

0+000 <target>:
[ ]+[0-9a-f]+:[ ]+fffff2b7[ ]+lui[ ]+t0,0xfffff
[ ]+[0-9a-f]+:[ ]+ffc2a903[ ]+lw[ ]+s2,-4\(t0\) # ffffffffffffeffc <addr_load>
[ ]+[0-9a-f]+:[ ]+ffffe337[ ]+lui[ ]+t1,0xffffe
[ ]+[0-9a-f]+:[ ]+ff332c23[ ]+sw[ ]+s3,-8\(t1\) # ffffffffffffdff8 <addr_store>
[ ]+[0-9a-f]+:[ ]+ffffd3b7[ ]+lui[ ]+t2,0xffffd
[ ]+[0-9a-f]+:[ ]+000380e7[ ]+jalr[ ]+t2 # ffffffffffffd000 <addr_jalr_1>
[ ]+[0-9a-f]+:[ ]+ffffce37[ ]+lui[ ]+t3,0xffffc
[ ]+[0-9a-f]+:[ ]+ff4e00e7[ ]+jalr[ ]+-12\(t3\) # ffffffffffffbff4 <addr_jalr_2>
[ ]+[0-9a-f]+:[ ]+ffffbeb7[ ]+lui[ ]+t4,0xffffb
[ ]+[0-9a-f]+:[ ]+000e8a67[ ]+jalr[ ]+s4,t4 # ffffffffffffb000 <addr_jalr_3>
[ ]+[0-9a-f]+:[ ]+ffffaf37[ ]+lui[ ]+t5,0xffffa
[ ]+[0-9a-f]+:[ ]+ff0f0a93[ ]+addi[ ]+s5,t5,-16 # ffffffffffff9ff0 <addr_loadaddr>
[ ]+[0-9a-f]+:[ ]+ffff9fb7[ ]+lui[ ]+t6,0xffff9
[ ]+[0-9a-f]+:[ ]+1fb1[ ]+addi[ ]+t6,t6,-20 # ffffffffffff8fec <addr_loadaddr_c>
[ ]+[0-9a-f]+:[ ]+ffff8b37[ ]+lui[ ]+s6,0xffff8
[ ]+[0-9a-f]+:[ ]+fe8b0b9b[ ]+addiw[ ]+s7,s6,-24 # ffffffffffff7fe8 <addr_loadaddr_w>
[ ]+[0-9a-f]+:[ ]+ffff7c37[ ]+lui[ ]+s8,0xffff7
[ ]+[0-9a-f]+:[ ]+3c11[ ]+addiw[ ]+s8,s8,-28 # ffffffffffff6fe4 <addr_loadaddr_w_c>
[ ]+[0-9a-f]+:[ ]+4001a283[ ]+lw[ ]+t0,1024\(gp\) # 600 <addr_rel_gp_pos>
[ ]+[0-9a-f]+:[ ]+c001a303[ ]+lw[ ]+t1,-1024\(gp\) # fffffffffffffe00 <addr_rel_gp_neg>
[ ]+[0-9a-f]+:[ ]+10002383[ ]+lw[ ]+t2,256\(zero\) # 100 <addr_rel_zero_pos>
[ ]+[0-9a-f]+:[ ]+80002e03[ ]+lw[ ]+t3,-2048\(zero\) # fffffffffffff800 <addr_rel_zero_neg>
[ ]+[0-9a-f]+:[ ]+10400ee7[ ]+jalr[ ]+t4,260\(zero\) # 104 <addr_jalr_rel_zero_pos>
[ ]+[0-9a-f]+:[ ]+80400f67[ ]+jalr[ ]+t5,-2044\(zero\) # fffffffffffff804 <addr_jalr_rel_zero_neg>
70 changes: 70 additions & 0 deletions gas/testsuite/gas/riscv/dis-addr-overflow.s
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.set __global_pointer$, 0x00000200

.ifdef rv64
topbase = 0xffffffff00000000
.else
topbase = 0
.endif

.set addr_load, topbase + 0xffffeffc # -0x1000 -4
.set addr_store, topbase + 0xffffdff8 # -0x2000 -8
.set addr_jalr_1, topbase + 0xffffd000 # -0x3000
.set addr_jalr_2, topbase + 0xffffbff4 # -0x4000 -12
.set addr_jalr_3, topbase + 0xffffb000 # -0x5000
.set addr_loadaddr, topbase + 0xffff9ff0 # -0x6000 -16
.set addr_loadaddr_c, topbase + 0xffff8fec # -0x7000 -20
.set addr_loadaddr_w, topbase + 0xffff7fe8 # -0x8000 -24
.set addr_loadaddr_w_c, topbase + 0xffff6fe4 # -0x9000 -28
.set addr_rel_gp_pos, 0x00000600 # __global_pointer$ + 0x400
.set addr_rel_gp_neg, topbase + 0xfffffe00 # __global_pointer$ - 0x400
.set addr_rel_zero_pos, 0x00000100
.set addr_rel_zero_neg, topbase + 0xfffff800 # -0x800
.set addr_jalr_rel_zero_pos, 0x00000104 # 0x104
.set addr_jalr_rel_zero_neg, topbase + 0xfffff804 # -0x7fc

target:
.option push
.option arch, -c
## Use hi_addr
# Load
lui t0, 0xfffff
lw s2, -4(t0)
# Store
lui t1, 0xffffe
sw s3, -8(t1)
# JALR (implicit destination, no offset)
lui t2, 0xffffd
jalr t2
# JALR (implicit destination, with offset)
lui t3, 0xffffc
jalr -12(t3)
# JALR (explicit destination, no offset)
lui t4, 0xffffb
jalr s4, t4
# ADDI (not compressed)
lui t5, 0xffffa
addi s5, t5, -16
# C.ADDI
lui t6, 0xffff9
.option pop
c.addi t6, -20
.ifdef rv64
.option push
.option arch, -c
# ADDIW (not compressed)
lui s6, 0xffff8
addiw s7, s6, -24
# C.ADDIW
lui s8, 0xffff7
.option pop
c.addiw s8, -28
.endif

# Use addresses relative to gp
lw t0, 0x400(gp)
lw t1, -0x400(gp)
# Use addresses relative to zero
lw t2, 0x100(zero)
lw t3, -0x800(zero)
jalr t4, 0x104(zero)
jalr t5, -0x7fc(zero)
11 changes: 11 additions & 0 deletions gas/testsuite/gas/riscv/dis-addr-topaddr-32.d
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#as: -march=rv32ic
#source: dis-addr-topaddr.s
#objdump: -d

.*: file format elf32-(little|big)riscv


Disassembly of section .text:

0+000 <target>:
[ ]+[0-9a-f]+:[ ]+fff00283[ ]+lb[ ]+t0,-1\(zero\) # ffffffff <addr_top>
11 changes: 11 additions & 0 deletions gas/testsuite/gas/riscv/dis-addr-topaddr-64.d
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#as: -march=rv64ic -defsym rv64=1
#source: dis-addr-topaddr.s
#objdump: -d

.*: file format elf64-(little|big)riscv


Disassembly of section .text:

0+000 <target>:
[ ]+[0-9a-f]+:[ ]+fff00283[ ]+lb[ ]+t0,-1\(zero\) # ffffffffffffffff <addr_top>
12 changes: 12 additions & 0 deletions gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d
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#as: -march=rv32i
#source: dis-addr-topaddr-gp.s
#objdump: -d

.*: file format elf32-(little|big)riscv


Disassembly of section .text:

0+000 <target>:
[ ]+[0-9a-f]+:[ ]+0051a283[ ]+lw[ ]+t0,5\(gp\) # 4 <addr_rel_gp_pos>
[ ]+[0-9a-f]+:[ ]+ffd1a303[ ]+lw[ ]+t1,-3\(gp\) # fffffffc <addr_rel_gp_neg>
12 changes: 12 additions & 0 deletions gas/testsuite/gas/riscv/dis-addr-topaddr-gp-64.d
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#as: -march=rv64i -defsym rv64=1
#source: dis-addr-topaddr-gp.s
#objdump: -d

.*: file format elf64-(little|big)riscv


Disassembly of section .text:

0+000 <target>:
[ ]+[0-9a-f]+:[ ]+0051a283[ ]+lw[ ]+t0,5\(gp\) # 4 <addr_rel_gp_pos>
[ ]+[0-9a-f]+:[ ]+ffd1a303[ ]+lw[ ]+t1,-3\(gp\) # fffffffffffffffc <addr_rel_gp_neg>
15 changes: 15 additions & 0 deletions gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s
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.ifdef rv64
topbase = 0xffffffff00000000
.else
topbase = 0
.endif

.set __global_pointer$, topbase + 0xffffffff # -1
.set addr_rel_gp_pos, 0x00000004 # +4
.set addr_rel_gp_neg, topbase + 0xfffffffc # -4

target:
# Use addresses relative to gp
# (gp is the highest address)
lw t0, +5(gp)
lw t1, -3(gp)
10 changes: 10 additions & 0 deletions gas/testsuite/gas/riscv/dis-addr-topaddr.s
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.ifdef rv64
topbase = 0xffffffff00000000
.else
topbase = 0
.endif

.set addr_top, topbase + 0xffffffff # -1

target:
lb t0, -1(zero)
2 changes: 1 addition & 1 deletion gas/testsuite/gas/riscv/lla32.d
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Expand Up @@ -14,6 +14,6 @@ Disassembly of section .text:
10: 00001537 lui a0,0x1
14: fff50513 addi a0,a0,-1 # fff <d>
18: 80000537 lui a0,0x80000
1c: fff50513 addi a0,a0,-1 # 7fffffff <h\+0x80000000>
1c: fff50513 addi a0,a0,-1 # 7fffffff <e>
20: 00000513 li a0,0
24: fff00513 li a0,-1
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