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Opcode Tidying (batch 1) #14

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Opcode Tidying (batch 1) #14

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99992e9
RISC-V: Add a space at the end of pinfo
a4lg Oct 18, 2022
c07f973
RISC-V: Fix obvious misalignments ('Zbb'/'Zba')
a4lg Sep 9, 2022
cc96536
RISC-V: Remove spaces in opcode entries
a4lg Sep 9, 2022
5688b2e
RISC-V: Remove unused instruction macros
a4lg May 20, 2022
dd30a55
RISC-V: Complete tidying up with SCALL and SBREAK
a4lg Feb 2, 2022
0e7cc66
RISC-V: Tidying up with fmv.w.x and fmv.x.w
a4lg Feb 2, 2022
ea1505c
RISC-V: Make alias instructions aliases
a4lg Jul 6, 2022
38d6a1d
RISC-V: Use defined mask and match values
a4lg Feb 2, 2022
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47 changes: 6 additions & 41 deletions include/opcode/riscv-opc.h
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Original file line number Diff line number Diff line change
Expand Up @@ -21,12 +21,6 @@
#ifndef RISCV_ENCODING_H
#define RISCV_ENCODING_H
/* Instruction opcode macros. */
#define MATCH_SLLI_RV32 0x1013
#define MASK_SLLI_RV32 0xfe00707f
#define MATCH_SRLI_RV32 0x5013
#define MASK_SRLI_RV32 0xfe00707f
#define MATCH_SRAI_RV32 0x40005013
#define MASK_SRAI_RV32 0xfe00707f
#define MATCH_FRFLAGS 0x102073
#define MASK_FRFLAGS 0xfffff07f
#define MATCH_FSFLAGS 0x101073
Expand Down Expand Up @@ -55,10 +49,6 @@
#define MASK_RDTIMEH 0xfffff07f
#define MATCH_RDINSTRETH 0xc8202073
#define MASK_RDINSTRETH 0xfffff07f
#define MATCH_SCALL 0x73
#define MASK_SCALL 0xffffffff
#define MATCH_SBREAK 0x100073
#define MASK_SBREAK 0xffffffff
#define MATCH_BEQ 0x63
#define MASK_BEQ 0x707f
#define MATCH_BNE 0x1063
Expand Down Expand Up @@ -365,8 +355,8 @@
#define MASK_FCVT_L_S 0xfff0007f
#define MATCH_FCVT_LU_S 0xc0300053
#define MASK_FCVT_LU_S 0xfff0007f
#define MATCH_FMV_X_S 0xe0000053
#define MASK_FMV_X_S 0xfff0707f
#define MATCH_FMV_X_W 0xe0000053
#define MASK_FMV_X_W 0xfff0707f
#define MATCH_FCLASS_S 0xe0001053
#define MASK_FCLASS_S 0xfff0707f
#define MATCH_FCVT_W_D 0xc2000053
Expand Down Expand Up @@ -399,8 +389,8 @@
#define MASK_FCVT_S_L 0xfff0007f
#define MATCH_FCVT_S_LU 0xd0300053
#define MASK_FCVT_S_LU 0xfff0007f
#define MATCH_FMV_S_X 0xf0000053
#define MASK_FMV_S_X 0xfff0707f
#define MATCH_FMV_W_X 0xf0000053
#define MASK_FMV_W_X 0xfff0707f
#define MATCH_FCVT_D_W 0xd2000053
#define MASK_FCVT_D_W 0xfff0007f
#define MATCH_FCVT_D_WU 0xd2100053
Expand Down Expand Up @@ -1723,20 +1713,6 @@
#define MASK_VWMACCSUVX 0xfc00707f
#define MATCH_VWMACCUSVX 0xf8006057
#define MASK_VWMACCUSVX 0xfc00707f
#define MATCH_VQMACCUVV 0xf0000057
#define MASK_VQMACCUVV 0xfc00707f
#define MATCH_VQMACCUVX 0xf0004057
#define MASK_VQMACCUVX 0xfc00707f
#define MATCH_VQMACCVV 0xf4000057
#define MASK_VQMACCVV 0xfc00707f
#define MATCH_VQMACCVX 0xf4004057
#define MASK_VQMACCVX 0xfc00707f
#define MATCH_VQMACCSUVV 0xfc000057
#define MASK_VQMACCSUVV 0xfc00707f
#define MATCH_VQMACCSUVX 0xfc004057
#define MASK_VQMACCSUVX 0xfc00707f
#define MATCH_VQMACCUSVX 0xf8004057
#define MASK_VQMACCUSVX 0xfc00707f
#define MATCH_VDIVVV 0x84002057
#define MASK_VDIVVV 0xfc00707f
#define MATCH_VDIVVX 0x84006057
Expand Down Expand Up @@ -2115,12 +2091,6 @@
#define MASK_VMV4RV 0xfe0ff07f
#define MATCH_VMV8RV 0x9e03b057
#define MASK_VMV8RV 0xfe0ff07f
#define MATCH_VDOTVV 0xe4000057
#define MASK_VDOTVV 0xfc00707f
#define MATCH_VDOTUVV 0xe0000057
#define MASK_VDOTUVV 0xfc00707f
#define MATCH_VFDOTVV 0xe4001057
#define MASK_VFDOTVV 0xfc00707f
/* Zvbb instructions. */
#define MATCH_VANDN_VV 0x4000057
#define MASK_VANDN_VV 0xfc00707f
Expand Down Expand Up @@ -2993,9 +2963,6 @@
#define CSR_VLENB 0xc22
#endif /* RISCV_ENCODING_H */
#ifdef DECLARE_INSN
DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32)
DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32)
DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS)
DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS)
DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI)
Expand All @@ -3010,8 +2977,6 @@ DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET)
DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH)
DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH)
DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH)
DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL)
DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK)
DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
Expand Down Expand Up @@ -3164,7 +3129,7 @@ DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W)
DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
Expand All @@ -3181,7 +3146,7 @@ DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X)
DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
Expand Down
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