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Draft Extension: Zicfiss and Zicfilp #121

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Draft Extension: Zicfiss and Zicfilp #121

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099ee33
UNRATIFIED RISC-V: Add 'Zicfiss' extension and its CSR
a4lg Nov 21, 2022
02c7f21
UNRATIFIED RISC-V: Add 'Zicfilp' extension
a4lg Nov 21, 2022
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15 changes: 15 additions & 0 deletions bfd/elfxx-riscv.c
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Expand Up @@ -1148,6 +1148,9 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"zhinx", "zhinxmin", check_implicit_always},
{"zhinxmin", "zfinx", check_implicit_always},
{"zfinx", "zicsr", check_implicit_always},
{"zicfiss", "zicsr", check_implicit_always},
{"zicfiss", "zimop", check_implicit_always},
{"zicfiss", "zcmop", check_implicit_always},
{"zk", "zkn", check_implicit_always},
{"zk", "zkr", check_implicit_always},
{"zk", "zkt", check_implicit_always},
Expand Down Expand Up @@ -1192,6 +1195,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"ssstateen", "zicsr", check_implicit_always},
{"sstc", "zicsr", check_implicit_always},
{"svadu", "zicsr", check_implicit_always},
/* Complex implications (that should be checked after others). */
/* Tail of the list. */
{NULL, NULL, NULL}
};

Expand Down Expand Up @@ -1252,6 +1257,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zicbom", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zicfilp", ISA_SPEC_CLASS_DRAFT, 0, 3, 0 },
{"zicfiss", ISA_SPEC_CLASS_DRAFT, 0, 3, 0 },
{"zicond", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zicsr", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
{"zicsr", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
Expand Down Expand Up @@ -2392,6 +2399,10 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "zicbop");
case INSN_CLASS_ZICBOZ:
return riscv_subset_supports (rps, "zicboz");
case INSN_CLASS_ZICFILP:
return riscv_subset_supports (rps, "zicfilp");
case INSN_CLASS_ZICFISS:
return riscv_subset_supports (rps, "zicfiss");
case INSN_CLASS_ZICOND:
return riscv_subset_supports (rps, "zicond");
case INSN_CLASS_ZICSR:
Expand Down Expand Up @@ -2599,6 +2610,10 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return "zicbop";
case INSN_CLASS_ZICBOZ:
return "zicboz";
case INSN_CLASS_ZICFILP:
return "zicfilp";
case INSN_CLASS_ZICFISS:
return "zicfiss";
case INSN_CLASS_ZICOND:
return "zicond";
case INSN_CLASS_ZICSR:
Expand Down
4 changes: 4 additions & 0 deletions gas/config/tc-riscv.c
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Expand Up @@ -67,6 +67,7 @@ enum riscv_csr_class
CSR_CLASS_I,
CSR_CLASS_I_32, /* rv32 only */
CSR_CLASS_F, /* f-ext only */
CSR_CLASS_ZICFISS, /* Zicfiss only */
CSR_CLASS_ZKR, /* zkr only */
CSR_CLASS_V, /* rvv only */
CSR_CLASS_DEBUG, /* debug CSR */
Expand Down Expand Up @@ -1042,6 +1043,9 @@ riscv_csr_address (const char *csr_name,
case CSR_CLASS_F:
extension = "f";
break;
case CSR_CLASS_ZICFISS:
extension = "zicfiss";
break;
case CSR_CLASS_ZKR:
extension = "zkr";
break;
Expand Down
1 change: 1 addition & 0 deletions gas/testsuite/gas/riscv/csr-dw-regnums.d
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Expand Up @@ -403,6 +403,7 @@ Contents of the .* section:
DW_CFA_offset_extended_sf: r4445 \(stimecmph\) at cfa\+1396
DW_CFA_offset_extended_sf: r4685 \(vstimecmp\) at cfa\+2356
DW_CFA_offset_extended_sf: r4701 \(vstimecmph\) at cfa\+2420
DW_CFA_offset_extended_sf: r4113 \(ssp\) at cfa\+68
DW_CFA_offset_extended_sf: r4163 \(utval\) at cfa\+268
DW_CFA_offset_extended_sf: r4419 \(stval\) at cfa\+1292
DW_CFA_offset_extended_sf: r4480 \(satp\) at cfa\+1536
Expand Down
2 changes: 2 additions & 0 deletions gas/testsuite/gas/riscv/csr-dw-regnums.s
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Expand Up @@ -405,6 +405,8 @@ _start:
.cfi_offset stimecmph, 1396
.cfi_offset vstimecmp, 2356
.cfi_offset vstimecmph, 2420
# Zicfiss extension
.cfi_offset ssp, 68
# dropped
.cfi_offset ubadaddr, 268 # aliases
.cfi_offset sbadaddr, 1292 # aliases
Expand Down
2 changes: 2 additions & 0 deletions gas/testsuite/gas/riscv/csr-version-1p10.d
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Expand Up @@ -895,3 +895,5 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+c2159073[ ]+csrw[ ]+vtype,a1
[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb
[ ]+[0-9a-f]+:[ ]+c2259073[ ]+csrw[ ]+vlenb,a1
[ ]+[0-9a-f]+:[ ]+01102573[ ]+csrr[ ]+a0,ssp
[ ]+[0-9a-f]+:[ ]+01159073[ ]+csrw[ ]+ssp,a1
4 changes: 4 additions & 0 deletions gas/testsuite/gas/riscv/csr-version-1p10.l
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Expand Up @@ -1613,3 +1613,7 @@
.*Info: macro .*
.*Warning: read-only CSR is written `csrw vlenb,a1'
.*Info: macro .*
.*Warning: invalid CSR `ssp', needs `zicfiss' extension
.*Info: macro .*
.*Warning: invalid CSR `ssp', needs `zicfiss' extension
.*Info: macro .*
2 changes: 2 additions & 0 deletions gas/testsuite/gas/riscv/csr-version-1p11.d
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Expand Up @@ -895,3 +895,5 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+c2159073[ ]+csrw[ ]+vtype,a1
[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb
[ ]+[0-9a-f]+:[ ]+c2259073[ ]+csrw[ ]+vlenb,a1
[ ]+[0-9a-f]+:[ ]+01102573[ ]+csrr[ ]+a0,ssp
[ ]+[0-9a-f]+:[ ]+01159073[ ]+csrw[ ]+ssp,a1
4 changes: 4 additions & 0 deletions gas/testsuite/gas/riscv/csr-version-1p11.l
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Expand Up @@ -1609,3 +1609,7 @@
.*Info: macro .*
.*Warning: read-only CSR is written `csrw vlenb,a1'
.*Info: macro .*
.*Warning: invalid CSR `ssp', needs `zicfiss' extension
.*Info: macro .*
.*Warning: invalid CSR `ssp', needs `zicfiss' extension
.*Info: macro .*
2 changes: 2 additions & 0 deletions gas/testsuite/gas/riscv/csr-version-1p12.d
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Expand Up @@ -895,3 +895,5 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+c2159073[ ]+csrw[ ]+vtype,a1
[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb
[ ]+[0-9a-f]+:[ ]+c2259073[ ]+csrw[ ]+vlenb,a1
[ ]+[0-9a-f]+:[ ]+01102573[ ]+csrr[ ]+a0,ssp
[ ]+[0-9a-f]+:[ ]+01159073[ ]+csrw[ ]+ssp,a1
4 changes: 4 additions & 0 deletions gas/testsuite/gas/riscv/csr-version-1p12.l
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Expand Up @@ -1373,3 +1373,7 @@
.*Info: macro .*
.*Warning: read-only CSR is written `csrw vlenb,a1'
.*Info: macro .*
.*Warning: invalid CSR `ssp', needs `zicfiss' extension
.*Info: macro .*
.*Warning: invalid CSR `ssp', needs `zicfiss' extension
.*Info: macro .*
2 changes: 2 additions & 0 deletions gas/testsuite/gas/riscv/csr-version-1p9p1.d
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Expand Up @@ -895,3 +895,5 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+c2159073[ ]+csrw[ ]+vtype,a1
[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb
[ ]+[0-9a-f]+:[ ]+c2259073[ ]+csrw[ ]+vlenb,a1
[ ]+[0-9a-f]+:[ ]+01102573[ ]+csrr[ ]+a0,ssp
[ ]+[0-9a-f]+:[ ]+01159073[ ]+csrw[ ]+ssp,a1
4 changes: 4 additions & 0 deletions gas/testsuite/gas/riscv/csr-version-1p9p1.l
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Expand Up @@ -1681,3 +1681,7 @@
.*Info: macro .*
.*Warning: read-only CSR is written `csrw vlenb,a1'
.*Info: macro .*
.*Warning: invalid CSR `ssp', needs `zicfiss' extension
.*Info: macro .*
.*Warning: invalid CSR `ssp', needs `zicfiss' extension
.*Info: macro .*
3 changes: 3 additions & 0 deletions gas/testsuite/gas/riscv/csr.s
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Expand Up @@ -510,3 +510,6 @@
csr vl
csr vtype
csr vlenb

# Control flow integrity (the Zicfiss extension)
csr ssp
13 changes: 13 additions & 0 deletions gas/testsuite/gas/riscv/zicfilp.d
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#as: -march=rv32ic_zicfilp
#objdump: -d

.*:[ ]+file format .*

Disassembly of section .text:

0+000 <target>:
[ ]+[0-9a-f]+:[ ]+12345017[ ]+lpad[ ]+0x12345
[ ]+[0-9a-f]+:[ ]+12345017[ ]+lpad[ ]+0x12345
[ ]+[0-9a-f]+:[ ]+0001[ ]+nop
[ ]+[0-9a-f]+:[ ]+f0123017[ ]+lpad[ ]+0xf0123
[ ]+[0-9a-f]+:[ ]+f0123017[ ]+lpad[ ]+0xf0123
14 changes: 14 additions & 0 deletions gas/testsuite/gas/riscv/zicfilp.s
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target:
# lpad LPL == auipc x0, LPL
lpad 0x12345
auipc zero, 0x12345

# Break alignment:
#
# Unaligned lpad causes illegal-instruction exception
# but must be disassembled (since alignment checking is a part of
# the lpad instruction operations).
c.nop

lpad 0xf0123
auipc zero, 0xf0123
10 changes: 10 additions & 0 deletions gas/testsuite/gas/riscv/zicfiss-32.d
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#as: -march=rv32ic_zicfiss
#objdump: -d

.*:[ ]+file format .*

Disassembly of section .text:

0+000 <target>:
[ ]+[0-9a-f]+:[ ]+81c040f3[ ]+sslw[ ]+ra
[ ]+[0-9a-f]+:[ ]+81c042f3[ ]+sslw[ ]+t0
3 changes: 3 additions & 0 deletions gas/testsuite/gas/riscv/zicfiss-32.s
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target:
sslw ra
sslw t0
10 changes: 10 additions & 0 deletions gas/testsuite/gas/riscv/zicfiss-64.d
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#as: -march=rv64ic_zicfiss
#objdump: -d

.*:[ ]+file format .*

Disassembly of section .text:

0+000 <target>:
[ ]+[0-9a-f]+:[ ]+81c040f3[ ]+ssld[ ]+ra
[ ]+[0-9a-f]+:[ ]+81c042f3[ ]+ssld[ ]+t0
3 changes: 3 additions & 0 deletions gas/testsuite/gas/riscv/zicfiss-64.s
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target:
ssld ra
ssld t0
2 changes: 2 additions & 0 deletions gas/testsuite/gas/riscv/zicfiss-fail-64.d
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#as: -march=rv64i_zicfiss
#error_output: zicfiss-fail-64.l
6 changes: 6 additions & 0 deletions gas/testsuite/gas/riscv/zicfiss-fail-64.l
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.*: Assembler messages:
.*: Error: illegal operands `ssld x0'
.*: Error: illegal operands `ssld x2'
.*: Error: illegal operands `ssld x31'
.*: Error: unrecognized opcode `sslw x1'
.*: Error: unrecognized opcode `sslw x5'
9 changes: 9 additions & 0 deletions gas/testsuite/gas/riscv/zicfiss-fail-64.s
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target:
# ssld: only x1 or x5 are allowed.
ssld x0
ssld x2
ssld x31

# sslw: only available on RV32.
sslw x1
sslw x5
2 changes: 2 additions & 0 deletions gas/testsuite/gas/riscv/zicfiss-fail.d
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#as: -march=rv32i_zicfiss
#error_output: zicfiss-fail.l
21 changes: 21 additions & 0 deletions gas/testsuite/gas/riscv/zicfiss-fail.l
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.*: Assembler messages:
.*: Error: illegal operands `sspush x0'
.*: Error: illegal operands `sspush x2'
.*: Error: illegal operands `sspush x31'
.*: Error: illegal operands `sspopchk x0'
.*: Error: illegal operands `sspopchk x2'
.*: Error: illegal operands `sspopchk x31'
.*: Error: illegal operands `sslw x0'
.*: Error: illegal operands `sslw x2'
.*: Error: illegal operands `sslw x31'
.*: Error: unrecognized opcode `ssld x1'
.*: Error: unrecognized opcode `ssld x5'
.*: Error: illegal operands `c\.sspush x5'
.*: Error: illegal operands `c\.sspopchk x1'
.*: Error: illegal operands `c\.sspush x0'
.*: Error: illegal operands `c\.sspush x2'
.*: Error: illegal operands `c\.sspush x31'
.*: Error: illegal operands `c\.sspopchk x0'
.*: Error: illegal operands `c\.sspopchk x2'
.*: Error: illegal operands `c\.sspopchk x31'
.*: Error: illegal operands `ssrdp x0'
29 changes: 29 additions & 0 deletions gas/testsuite/gas/riscv/zicfiss-fail.s
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# Tested with RV32
target:
# sspush / sspopchk / sslw: only x1 or x5 are allowed.
sspush x0
sspush x2
sspush x31
sspopchk x0
sspopchk x2
sspopchk x31
sslw x0
sslw x2
sslw x31

# ssld: only available on RV64.
ssld x1
ssld x5

# c.sspush x1 / c.sspopchk x5: all other GPRs are not allowed.
c.sspush x5
c.sspopchk x1
c.sspush x0
c.sspush x2
c.sspush x31
c.sspopchk x0
c.sspopchk x2
c.sspopchk x31

# ssrdp: rd must not be x0.
ssrdp x0
19 changes: 19 additions & 0 deletions gas/testsuite/gas/riscv/zicfiss-mop-32.d
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#as: -march=rv32ic_zicfiss
#source: zicfiss-mop.s
#objdump: -d

.*:[ ]+file format .*

Disassembly of section .text:

0+000 <target>:
[ ]+[0-9a-f]+:[ ]+81c040f3[ ]+sslw[ ]+ra
[ ]+[0-9a-f]+:[ ]+81c042f3[ ]+sslw[ ]+t0
[ ]+[0-9a-f]+:[ ]+81c0c073[ ]+sspopchk[ ]+ra
[ ]+[0-9a-f]+:[ ]+81c2c073[ ]+sspopchk[ ]+t0
[ ]+[0-9a-f]+:[ ]+81d04ff3[ ]+ssrdp[ ]+t6
[ ]+[0-9a-f]+:[ ]+82104073[ ]+sspush[ ]+ra
[ ]+[0-9a-f]+:[ ]+82504073[ ]+sspush[ ]+t0
[ ]+[0-9a-f]+:[ ]+6081[ ]+sspush[ ]+ra
[ ]+[0-9a-f]+:[ ]+6181[ ]+ssincp
[ ]+[0-9a-f]+:[ ]+6281[ ]+sspopchk[ ]+t0
19 changes: 19 additions & 0 deletions gas/testsuite/gas/riscv/zicfiss-mop-64.d
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#as: -march=rv64ic_zicfiss
#source: zicfiss-mop.s
#objdump: -d

.*:[ ]+file format .*

Disassembly of section .text:

0+000 <target>:
[ ]+[0-9a-f]+:[ ]+81c040f3[ ]+ssld[ ]+ra
[ ]+[0-9a-f]+:[ ]+81c042f3[ ]+ssld[ ]+t0
[ ]+[0-9a-f]+:[ ]+81c0c073[ ]+sspopchk[ ]+ra
[ ]+[0-9a-f]+:[ ]+81c2c073[ ]+sspopchk[ ]+t0
[ ]+[0-9a-f]+:[ ]+81d04ff3[ ]+ssrdp[ ]+t6
[ ]+[0-9a-f]+:[ ]+82104073[ ]+sspush[ ]+ra
[ ]+[0-9a-f]+:[ ]+82504073[ ]+sspush[ ]+t0
[ ]+[0-9a-f]+:[ ]+6081[ ]+sspush[ ]+ra
[ ]+[0-9a-f]+:[ ]+6181[ ]+ssincp
[ ]+[0-9a-f]+:[ ]+6281[ ]+sspopchk[ ]+t0
24 changes: 24 additions & 0 deletions gas/testsuite/gas/riscv/zicfiss-mop.s
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target:
# ssl[wd] x1 == mop.r.0 x1, x0
# ssl[wd] x5 == mop.r.0 x5, x0
# sspopchk x1 == mop.r.0 x0, x1
# sspopchk x5 == mop.r.0 x0, x5
mop.r.0 ra, zero
mop.r.0 t0, zero
mop.r.0 zero, ra
mop.r.0 zero, t0

# ssrdp rd == mop.r.1 rd, x0 (rd != 0)
mop.r.1 x31, zero

# sspush x1 == mop.rr.0 x0, x0, x1
# sspush x5 == mop.rr.0 x0, x0, x5
mop.rr.0 zero, zero, ra
mop.rr.0 zero, zero, t0

# c.sspush x1 == c.mop.0
# c.ssincp == c.mop.1
# c.sspopchk x5 == c.mop.2
c.mop.0
c.mop.1
c.mop.2
20 changes: 20 additions & 0 deletions gas/testsuite/gas/riscv/zicfiss-na.d
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#as: -march=rv32i_zicfiss
#source: zicfiss.s
#objdump: -d -M no-aliases

.*:[ ]+file format .*

Disassembly of section .text:

0+000 <target>:
[ ]+[0-9a-f]+:[ ]+6081[ ]+c\.sspush[ ]+ra
[ ]+[0-9a-f]+:[ ]+6081[ ]+c\.sspush[ ]+ra
[ ]+[0-9a-f]+:[ ]+6281[ ]+c\.sspopchk[ ]+t0
[ ]+[0-9a-f]+:[ ]+6281[ ]+c\.sspopchk[ ]+t0
[ ]+[0-9a-f]+:[ ]+6081[ ]+c\.sspush[ ]+ra
[ ]+[0-9a-f]+:[ ]+82504073[ ]+sspush[ ]+t0
[ ]+[0-9a-f]+:[ ]+81c0c073[ ]+sspopchk[ ]+ra
[ ]+[0-9a-f]+:[ ]+6281[ ]+c\.sspopchk[ ]+t0
[ ]+[0-9a-f]+:[ ]+6181[ ]+c\.ssincp
[ ]+[0-9a-f]+:[ ]+81d042f3[ ]+ssrdp[ ]+t0
[ ]+[0-9a-f]+:[ ]+81d04573[ ]+ssrdp[ ]+a0
19 changes: 19 additions & 0 deletions gas/testsuite/gas/riscv/zicfiss.d
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#as: -march=rv32i_zicfiss
#objdump: -d

.*:[ ]+file format .*

Disassembly of section .text:

0+000 <target>:
[ ]+[0-9a-f]+:[ ]+6081[ ]+sspush[ ]+ra
[ ]+[0-9a-f]+:[ ]+6081[ ]+sspush[ ]+ra
[ ]+[0-9a-f]+:[ ]+6281[ ]+sspopchk[ ]+t0
[ ]+[0-9a-f]+:[ ]+6281[ ]+sspopchk[ ]+t0
[ ]+[0-9a-f]+:[ ]+6081[ ]+sspush[ ]+ra
[ ]+[0-9a-f]+:[ ]+82504073[ ]+sspush[ ]+t0
[ ]+[0-9a-f]+:[ ]+81c0c073[ ]+sspopchk[ ]+ra
[ ]+[0-9a-f]+:[ ]+6281[ ]+sspopchk[ ]+t0
[ ]+[0-9a-f]+:[ ]+6181[ ]+ssincp
[ ]+[0-9a-f]+:[ ]+81d042f3[ ]+ssrdp[ ]+t0
[ ]+[0-9a-f]+:[ ]+81d04573[ ]+ssrdp[ ]+a0
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