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RISC-V: Fallback on faster hash table
Although it does not have a problem on current GNU Binutils implementation, if the custom vendor implements an instruction which spans across multiple major opcodes (e.g. uses both CUSTOM_0 and CUSTOM_1 in a *single* custom instruction), the original assumption of the sorted hash table breaks. In this case, this commit enables the fallback mode to disable all optimizations except filtering macros out. Note that, if a such instruction (that disables this disassembler optimization) is upstreamed to Binutils, a separate solution will be required to avoid major performance degradation when such instruction is not used. The intent of this commit is to make a room for custom vendors to implement such instructions in *their* tree without causing disassembler problems. opcodes/ChangeLog: * riscv-dis.c (is_riscv_hash_fallback) New. (build_riscv_opcodes_hash_table): If an instruction spans across multiple major opcodes, enable fallback mode and disable sorting. (riscv_disassemble_insn): If the fallback mode is enabled, scan through all instructions instead of scanning only instruction entries matching the hash value.