RISC-V: Add RV64E support to GDB

Since RV32E and RV64E are ratified, RV64E is no longer invalid. So, this commit adds RV64E support for various parts.
a4lg · Aug 15, 2023 · bc9cc57 · bc9cc57
1 parent 472c67e
commit bc9cc57
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Showing 6 changed files with 77 additions and 11 deletions.
diff --git a/gdb/arch/riscv.c b/gdb/arch/riscv.c
@@ -25,6 +25,7 @@
 #include "../features/riscv/32bit-fpu.c"
 #include "../features/riscv/64bit-fpu.c"
 #include "../features/riscv/rv32e-xregs.c"
+#include "../features/riscv/rv64e-xregs.c"
 
 #ifndef GDBSERVER
 #define STATIC_IN_GDB static
@@ -51,7 +52,12 @@ riscv_create_target_description (const struct riscv_gdbarch_features features)
 	arch_name.append (":rv32i");
     }
   else if (features.xlen == 8)
-    arch_name.append (":rv64i");
+    {
+      if (features.embedded)
+	arch_name.append (":rv64e");
+      else
+	arch_name.append (":rv64i");
+    }
   else if (features.xlen == 16)
     arch_name.append (":rv128i");
 
@@ -76,7 +82,12 @@ riscv_create_target_description (const struct riscv_gdbarch_features features)
 	regnum = create_feature_riscv_32bit_cpu (tdesc.get (), regnum);
     }
   else if (features.xlen == 8)
-    regnum = create_feature_riscv_64bit_cpu (tdesc.get (), regnum);
+    {
+      if (features.embedded)
+	regnum = create_feature_riscv_rv64e_xregs (tdesc.get (), regnum);
+      else
+	regnum = create_feature_riscv_64bit_cpu (tdesc.get (), regnum);
+    }
 
   /* For now we only support creating 32-bit or 64-bit f-registers.  */
   if (features.flen == 4)

diff --git a/gdb/arch/riscv.h b/gdb/arch/riscv.h
@@ -53,7 +53,7 @@ struct riscv_gdbarch_features
      vector size.  */
   int vlen = 0;
 
-  /* When true this target is RV32E.  */
+  /* When true this target is RV32E or RV64E.  */
   bool embedded = false;
 
   /* Track if the target description has an fcsr, fflags, and frm

diff --git a/gdb/features/Makefile b/gdb/features/Makefile
@@ -238,6 +238,7 @@ FEATURE_XMLFILES = aarch64-core.xml \
 	loongarch/base64.xml \
 	loongarch/fpu.xml \
 	riscv/rv32e-xregs.xml \
+	riscv/rv64e-xregs.xml \
 	riscv/32bit-cpu.xml \
 	riscv/32bit-fpu.xml \
 	riscv/64bit-cpu.xml \

diff --git a/gdb/features/riscv/rv64e-xregs.c b/gdb/features/riscv/rv64e-xregs.c
@@ -0,0 +1,30 @@
+/* THIS FILE IS GENERATED.  -*- buffer-read-only: t -*- vi:set ro:
+  Original: rv64e-xregs.xml */
+
+#include "gdbsupport/tdesc.h"
+
+static int
+create_feature_riscv_rv64e_xregs (struct target_desc *result, long regnum)
+{
+  struct tdesc_feature *feature;
+
+  feature = tdesc_create_feature (result, "org.gnu.gdb.riscv.cpu");
+  tdesc_create_reg (feature, "zero", regnum++, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "ra", regnum++, 1, NULL, 64, "code_ptr");
+  tdesc_create_reg (feature, "sp", regnum++, 1, NULL, 64, "data_ptr");
+  tdesc_create_reg (feature, "gp", regnum++, 1, NULL, 64, "data_ptr");
+  tdesc_create_reg (feature, "tp", regnum++, 1, NULL, 64, "data_ptr");
+  tdesc_create_reg (feature, "t0", regnum++, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "t1", regnum++, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "t2", regnum++, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "fp", regnum++, 1, NULL, 64, "data_ptr");
+  tdesc_create_reg (feature, "s1", regnum++, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "a0", regnum++, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "a1", regnum++, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "a2", regnum++, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "a3", regnum++, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "a4", regnum++, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "a5", regnum++, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "pc", regnum++, 1, NULL, 64, "code_ptr");
+  return regnum;
+}
diff --git a/gdb/features/riscv/rv64e-xregs.xml b/gdb/features/riscv/rv64e-xregs.xml
@@ -0,0 +1,31 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018-2023 Free Software Foundation, Inc.
+
+     Copying and distribution of this file, with or without modification,
+     are permitted in any medium without royalty provided the copyright
+     notice and this notice are preserved.  -->
+
+<!-- Register numbers are hard-coded in order to maintain backward
+     compatibility with older versions of tools that didn't use xml
+     register descriptions.  -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.riscv.cpu">
+  <reg name="zero" bitsize="64" type="int" regnum="0"/>
+  <reg name="ra" bitsize="64" type="code_ptr"/>
+  <reg name="sp" bitsize="64" type="data_ptr"/>
+  <reg name="gp" bitsize="64" type="data_ptr"/>
+  <reg name="tp" bitsize="64" type="data_ptr"/>
+  <reg name="t0" bitsize="64" type="int"/>
+  <reg name="t1" bitsize="64" type="int"/>
+  <reg name="t2" bitsize="64" type="int"/>
+  <reg name="fp" bitsize="64" type="data_ptr"/>
+  <reg name="s1" bitsize="64" type="int"/>
+  <reg name="a0" bitsize="64" type="int"/>
+  <reg name="a1" bitsize="64" type="int"/>
+  <reg name="a2" bitsize="64" type="int"/>
+  <reg name="a3" bitsize="64" type="int"/>
+  <reg name="a4" bitsize="64" type="int"/>
+  <reg name="a5" bitsize="64" type="int"/>
+  <reg name="pc" bitsize="64" type="code_ptr"/>
+</feature>
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
@@ -3847,14 +3847,7 @@ riscv_features_from_bfd (const bfd *abfd)
 	features.flen = 4;
 
       if (e_flags & EF_RISCV_RVE)
-	{
-	  if (features.xlen == 8)
-	    {
-	      warning (_("64-bit ELF with RV32E flag set!  Assuming 32-bit"));
-	      features.xlen = 4;
-	    }
-	  features.embedded = true;
-	}
+	features.embedded = true;
     }
 
   return features;