RISC-V: Cache instruction support

As the author mentioned in a previous commit ("RISC-V: Minimize disassembler
state initialization"), calling `riscv_subset_supports' repeatedly harms the
performance in a measurable way (about 3-13% in total).

As a simple solution, this commit now caches instruction class support as a
signed char array.

It is expected to have 5-7% performance improvements when disassembling
linked RISC-V ELF programs using `objdump'.

include/ChangeLog:

	* opcode/riscv.h (enum riscv_insn_class): Add `NUM_INSN_CLASSES'.

opcodes/ChangeLog:

	* riscv-dis.c (riscv_insn_support_cache) New.
	(init_riscv_dis_state_for_arch): Clear the instruction support
	cache.  (riscv_disassemble_insn): Cache the instruction support.

include/opcode/riscv.h

@@ -397,6 +397,8 @@ enum riscv_insn_class
   INSN_CLASS_ZICBOP,
   INSN_CLASS_ZICBOZ,
   INSN_CLASS_H,
+
+  NUM_INSN_CLASSES,
 };
 
 /* This structure holds information for a particular instruction.  */

opcodes/riscv-dis.c

@@ -91,6 +91,9 @@ static bool no_aliases = false;
 /* If set, disassemble with numeric register names.  */
 static bool is_numeric = false;
 
+/* Instruction support cache.  */
+static signed char riscv_insn_support_cache[NUM_INSN_CLASSES];
+
 static void init_riscv_dis_state_for_arch (void);
 static void init_riscv_dis_state_for_arch_and_options (void);
 
@@ -316,6 +319,9 @@ static void
 init_riscv_dis_state_for_arch (void)
 {
   is_arch_changed = true;
+  /* Clear instruction support cache.  */
+  for (size_t i = 0; i < NUM_INSN_CLASSES; i++)
+    riscv_insn_support_cache[i] = 0;
 }
 
 static void
@@ -822,7 +828,14 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
       if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen))
 	continue;
       /* Is this instruction supported by the current architecture?  */
-      if (!riscv_multi_subset_supports (&riscv_rps_dis, op->insn_class))
+      if (riscv_insn_support_cache[op->insn_class] == 0)
+	{
+	  riscv_insn_support_cache[op->insn_class]
+	      = riscv_multi_subset_supports (&riscv_rps_dis, op->insn_class)
+		    ? +1
+		    : -1;
+	}
+      if (riscv_insn_support_cache[op->insn_class] < 0)
 	continue;
 
       matched_op = op;