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RISC-V: Reorganize and enhance Zfinx tests
This commit adds certain test cases for Zfinx/Zdinx/Zqinx extensions and reorganizes them, fixing coding style while improving coverage. This is partially based on jiawei's Zhinx testcases. gas/ChangeLog: * testsuite/gas/riscv/zfinx.s: Use different registers for better encode space testing / make indentation consistent / add tests for instruction with rounding mode. * testsuite/gas/riscv/zfinx.d: Likewise. * testsuite/gas/riscv/zdinx.s: Use different registers for better encode space testing / make indentation consistent / add tests for instruction with rounding mode. * testsuite/gas/riscv/zdinx.d: Likewise. * testsuite/gas/riscv/zqinx.s: Use different registers for better encode space testing / make indentation consistent / add tests for instruction with rounding mode / use even-numbered registers to use valid register pairs. * testsuite/gas/riscv/zqinx.d: Likewise. Signed-off-by: Tsukasa OI <[email protected]> Signed-off-by: jiawei <[email protected]>
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target: | ||
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fcvt.w.d a0, a1 | ||
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target: | ||
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fmadd.s a0, a1, a2, a3 | ||
fmadd.s a0, a1, a2, a3, rne | ||
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fnmadd.s a0, a1, a2, a3, rne | ||
fmsub.s a0, a1, a2, a3 | ||
fmsub.s a0, a1, a2, a3, rne | ||
fnmsub.s a0, a1, a2, a3 | ||
fnmsub.s a0, a1, a2, a3, rne | ||
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fcvt.w.s a0, a1 | ||
fcvt.w.s a0, a1, rne | ||
fcvt.wu.s a0, a1 | ||
fcvt.wu.s a0, a1, rne | ||
fcvt.l.s a0, a1 | ||
fcvt.l.s a0, a1, rne | ||
fcvt.lu.s a0, a1 | ||
fcvt.lu.s a0, a1, rne | ||
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fsgnj.s a0, a1, a2 | ||
fcvt.s.lu a0, a1, rne | ||
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