RISC-V: Validate 'Zdinx'/'Zqinx' register pairs

This commit adds floating point register number validation on
'Zdinx'/'Zqinx' extensions by separating handling on 'D'/'Q' and 'Zdinx'
/'Zqinx' extensions.

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Reflect new
	instruction classes. (riscv_multi_subset_supports_ext): Reflect
	new instruction classes.

gas/ChangeLog:

	* config/tc-riscv.c (riscv_ip): Add extension variant handling
	related to 'D'/'Zdinx' and 'Q'/'Zqinx'.
	* testsuite/gas/riscv/zdinx-32-regpair.s: Test RV32_Zdinx
	register pairs.
	* testsuite/gas/riscv/zdinx-32-regpair.d: Likewise.
	* testsuite/gas/riscv/zdinx-32-regpair-dis.s: New test to make
	sure that invalid encoding is disassembled with invalid operands.
	* testsuite/gas/riscv/zdinx-32-regpair-dis.d: Likewise.
	* testsuite/gas/riscv/zdinx-32-regpair-fail.s: Test RV32_Zdinx
	register pairs but expect to fail.
	* testsuite/gas/riscv/zdinx-32-regpair-fail.d: Likewise.
	* testsuite/gas/riscv/zdinx-32-regpair-fail.l: Likewise.
	* testsuite/gas/riscv/zdinx-zhinxmin-32-regpair.s: Test
	RV32_Zdinx_Zhinxmin register pairs.
	* testsuite/gas/riscv/zdinx-zhinxmin-32-regpair.d: Likewise.
	* testsuite/gas/riscv/zdinx-zhinxmin-32-regpair-fail.s: Test
	RV32_Zdinx_Zhinxmin register pairs but expect to fail.
	* testsuite/gas/riscv/zdinx-zhinxmin-32-regpair-fail.d: Likewise.
	* testsuite/gas/riscv/zdinx-zhinxmin-32-regpair-fail.l: Likewise.
	* testsuite/gas/riscv/zqinx-64-regpair.s: Test RV64_Zqinx
	register pairs.
	* testsuite/gas/riscv/zqinx-64-regpair.d: Likewise.
	* testsuite/gas/riscv/zqinx-64-regpair-dis.s: New test to make
	sure that invalid encoding is disassembled with invalid operands.
	* testsuite/gas/riscv/zqinx-64-regpair-dis.d: Likewise.
	* testsuite/gas/riscv/zqinx-64-regpair-fail.s: Test RV64_Zqinx
	register pairs but expect to fail.
	* testsuite/gas/riscv/zqinx-64-regpair-fail.d: Likewise.
	* testsuite/gas/riscv/zqinx-64-regpair-fail.l: Likewise.
	* testsuite/gas/riscv/zqinx-zhinxmin-64-regpair.s: Test
	RV64_Zqinx_Zhinxmin register pairs.
	* testsuite/gas/riscv/zqinx-zhinxmin-64-regpair.d: Likewise.
	* testsuite/gas/riscv/zqinx-zhinxmin-64-regpair-fail.s: Test
	RV64_Zqinx_Zhinxmin register pairs but expect to fail.
	* testsuite/gas/riscv/zqinx-zhinxmin-64-regpair-fail.d: Likewise.
	* testsuite/gas/riscv/zqinx-zhinxmin-64-regpair-fail.l: Likewise.
	* testsuite/gas/riscv/zqinx-32-regpair.s: Test RV32_Zqinx
	register pairs and quad-register groups.
	* testsuite/gas/riscv/zqinx-32-regpair.d: Likewise.
	* testsuite/gas/riscv/zqinx-32-regpair-dis.s: New test to make
	sure that invalid encoding is disassembled with invalid operands.
	* testsuite/gas/riscv/zqinx-32-regpair-dis.d: Likewise.
	* testsuite/gas/riscv/zqinx-32-regpair-fail.s: Test RV32_Zqinx
	register pairs and quad-register groups but expect to fail.
	* testsuite/gas/riscv/zqinx-32-regpair-fail.d: Likewise.
	* testsuite/gas/riscv/zqinx-32-regpair-fail.l: Likewise.
	* testsuite/gas/riscv/zqinx-zhinxmin-32-regpair.s: Test
	RV32_Zqinx_Zhinxmin register pairs and quad-register groups.
	* testsuite/gas/riscv/zqinx-zhinxmin-32-regpair.d: Likewise.
	* testsuite/gas/riscv/zqinx-zhinxmin-32-regpair-fail.s: Test
	RV32_Zqinx_Zhinxmin register pairs and quad-register groups
	but expect to fail.
	* testsuite/gas/riscv/zqinx-zhinxmin-32-regpair-fail.d: Likewise.
	* testsuite/gas/riscv/zqinx-zhinxmin-32-regpair-fail.l: Likewise.

include/ChangeLog:

	* opcode/riscv.h (enum riscv_insn_class): Rename generic classes
	INSN_CLASS_ZFHMIN_AND_{D,Q} to INSN_CLASS_ZFHMIN_AND_{D,Q}_OR_X.
	Add narrow instruction classes INSN_CLASS_Z{D,Q}INX,
	INSN_CLASS_ZFHMIN_AND_{D,Q} and INSN_CLASS_ZHINXMIN_AND_Z{D,Q}INX.

opcodes/ChangeLog:

	* riscv-opc.c: Adjust indentation.
	(riscv_opcodes): Use new instruction classes and
	INSN_HAS_EXT_VARS.  Split entries to 'D'/'Zdinx' or 'Q'/'Zqinx'
	if necessary.

bfd/elfxx-riscv.c

@@ -2338,6 +2338,10 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
     case INSN_CLASS_Q_OR_ZQINX:
       return (riscv_subset_supports (rps, "q")
 	      || riscv_subset_supports (rps, "zqinx"));
+    case INSN_CLASS_ZDINX:
+      return riscv_subset_supports (rps, "zdinx");
+    case INSN_CLASS_ZQINX:
+      return riscv_subset_supports (rps, "zqinx");
     case INSN_CLASS_ZFH_OR_ZHINX:
       return (riscv_subset_supports (rps, "zfh")
 	      || riscv_subset_supports (rps, "zhinx"));
@@ -2346,16 +2350,28 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
     case INSN_CLASS_ZFHMIN_OR_ZHINXMIN:
       return (riscv_subset_supports (rps, "zfhmin")
 	      || riscv_subset_supports (rps, "zhinxmin"));
-    case INSN_CLASS_ZFHMIN_AND_D:
+    case INSN_CLASS_ZFHMIN_AND_D_OR_X:
       return ((riscv_subset_supports (rps, "zfhmin")
 	       && riscv_subset_supports (rps, "d"))
 	      || (riscv_subset_supports (rps, "zhinxmin")
 		  && riscv_subset_supports (rps, "zdinx")));
-    case INSN_CLASS_ZFHMIN_AND_Q:
+    case INSN_CLASS_ZFHMIN_AND_Q_OR_X:
       return ((riscv_subset_supports (rps, "zfhmin")
 	       && riscv_subset_supports (rps, "q"))
 	      || (riscv_subset_supports (rps, "zhinxmin")
 		  && riscv_subset_supports (rps, "zqinx")));
+    case INSN_CLASS_ZFHMIN_AND_D:
+      return ((riscv_subset_supports (rps, "zfhmin")
+	       && riscv_subset_supports (rps, "d")));
+    case INSN_CLASS_ZFHMIN_AND_Q:
+      return ((riscv_subset_supports (rps, "zfhmin")
+	       && riscv_subset_supports (rps, "q")));
+    case INSN_CLASS_ZHINXMIN_AND_ZDINX:
+      return (riscv_subset_supports (rps, "zhinxmin")
+	      && riscv_subset_supports (rps, "zdinx"));
+    case INSN_CLASS_ZHINXMIN_AND_ZQINX:
+      return (riscv_subset_supports (rps, "zhinxmin")
+	      && riscv_subset_supports (rps, "zqinx"));
     case INSN_CLASS_ZBA:
       return riscv_subset_supports (rps, "zba");
     case INSN_CLASS_ZBB:
@@ -2485,13 +2501,17 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("d' or `zdinx");
     case INSN_CLASS_Q_OR_ZQINX:
       return _("q' or `zqinx");
+    case INSN_CLASS_ZDINX:
+      return "zdinx";
+    case INSN_CLASS_ZQINX:
+      return "zqinx";
     case INSN_CLASS_ZFH_OR_ZHINX:
       return _("zfh' or `zhinx");
     case INSN_CLASS_ZFHMIN:
       return "zfhmin";
     case INSN_CLASS_ZFHMIN_OR_ZHINXMIN:
       return _("zfhmin' or `zhinxmin");
-    case INSN_CLASS_ZFHMIN_AND_D:
+    case INSN_CLASS_ZFHMIN_AND_D_OR_X:
       if (riscv_subset_supports (rps, "zfhmin"))
 	return "d";
       else if (riscv_subset_supports (rps, "d"))
@@ -2502,7 +2522,7 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
 	return "zhinxmin";
       else
 	return _("zfhmin' and `d', or `zhinxmin' and `zdinx");
-    case INSN_CLASS_ZFHMIN_AND_Q:
+    case INSN_CLASS_ZFHMIN_AND_Q_OR_X:
       if (riscv_subset_supports (rps, "zfhmin"))
 	return "q";
       else if (riscv_subset_supports (rps, "q"))
@@ -2513,6 +2533,38 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
 	return "zhinxmin";
       else
 	return _("zfhmin' and `q', or `zhinxmin' and `zqinx");
+    case INSN_CLASS_ZFHMIN_AND_D:
+      if (!riscv_subset_supports (rps, "zfhmin")
+	  && !riscv_subset_supports (rps, "d"))
+	return _("zfhmin' and `d");
+      else if (!riscv_subset_supports (rps, "zfhmin"))
+	return "zfhmin";
+      else
+	return "d";
+    case INSN_CLASS_ZFHMIN_AND_Q:
+      if (!riscv_subset_supports (rps, "zfhmin")
+	  && !riscv_subset_supports (rps, "q"))
+	return _("zfhmin' and `q");
+      else if (!riscv_subset_supports (rps, "zfhmin"))
+	return "zfhmin";
+      else
+	return "q";
+    case INSN_CLASS_ZHINXMIN_AND_ZDINX:
+      if (!riscv_subset_supports (rps, "zhinxmin")
+	  && !riscv_subset_supports (rps, "zdinx"))
+	return _("zhinxmin' and `zdinx");
+      else if (!riscv_subset_supports (rps, "zhinxmin"))
+	return "zhinxmin";
+      else
+	return "zdinx";
+    case INSN_CLASS_ZHINXMIN_AND_ZQINX:
+      if (!riscv_subset_supports (rps, "zhinxmin")
+	  && !riscv_subset_supports (rps, "zqinx"))
+	return _("zhinxmin' and `zqinx");
+      else if (!riscv_subset_supports (rps, "zhinxmin"))
+	return "zhinxmin";
+      else
+	return "zqinx";
     case INSN_CLASS_ZBA:
       return "zba";
     case INSN_CLASS_ZBB:

gas/config/tc-riscv.c

@@ -2420,6 +2420,22 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 	      */
 	      switch (insn_class)
 		{
+		case INSN_CLASS_D:
+		case INSN_CLASS_ZDINX:
+		  insn_class = INSN_CLASS_D_OR_ZDINX;
+		  break;
+		case INSN_CLASS_Q:
+		case INSN_CLASS_ZQINX:
+		  insn_class = INSN_CLASS_Q_OR_ZQINX;
+		  break;
+		case INSN_CLASS_ZFHMIN_AND_D:
+		case INSN_CLASS_ZHINXMIN_AND_ZDINX:
+		  insn_class = INSN_CLASS_ZFHMIN_AND_D_OR_X;
+		  break;
+		case INSN_CLASS_ZFHMIN_AND_Q:
+		case INSN_CLASS_ZHINXMIN_AND_ZQINX:
+		  insn_class = INSN_CLASS_ZFHMIN_AND_Q_OR_X;
+		  break;
 		default:
 		  break;
 		}

gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d

@@ -0,0 +1,10 @@
+#as: -march=rv32i_zdinx
+#objdump: -dr -Mnumeric
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+02627153[ 	]+fadd.d[ 	]+x2,x4,x6
+[ 	]+[0-9a-f]+:[ 	]+0272f1d3[ 	]+fadd.d[ 	]+invalid3,invalid5,invalid7

gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s

@@ -0,0 +1,5 @@
+target:
+	# fadd.d x2, x4, x6
+	.insn r	OP_FP, 0x7, 0x01, x2, x4, x6
+	# fadd.d x3, x5, x7 (invalid)
+	.insn r	OP_FP, 0x7, 0x01, x3, x5, x7

gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d

@@ -0,0 +1,2 @@
+#as: -march=rv32i_zdinx
+#error_output: zdinx-32-regpair-fail.l

gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l

@@ -0,0 +1,111 @@
+.*Assembler messages:
+.*Error: illegal operands `fadd\.d a1,a2,a4'
+.*Error: illegal operands `fadd\.d a1,a2,a4,rne'
+.*Error: illegal operands `fadd\.d a0,a1,a4'
+.*Error: illegal operands `fadd\.d a0,a1,a4,rne'
+.*Error: illegal operands `fadd\.d a0,a2,a1'
+.*Error: illegal operands `fadd\.d a0,a2,a1,rne'
+.*Error: illegal operands `fsub\.d a1,a2,a4'
+.*Error: illegal operands `fsub\.d a1,a2,a4,rne'
+.*Error: illegal operands `fsub\.d a0,a1,a4'
+.*Error: illegal operands `fsub\.d a0,a1,a4,rne'
+.*Error: illegal operands `fsub\.d a0,a2,a1'
+.*Error: illegal operands `fsub\.d a0,a2,a1,rne'
+.*Error: illegal operands `fmul\.d a1,a2,a4'
+.*Error: illegal operands `fmul\.d a1,a2,a4,rne'
+.*Error: illegal operands `fmul\.d a0,a1,a4'
+.*Error: illegal operands `fmul\.d a0,a1,a4,rne'
+.*Error: illegal operands `fmul\.d a0,a2,a1'
+.*Error: illegal operands `fmul\.d a0,a2,a1,rne'
+.*Error: illegal operands `fdiv\.d a1,a2,a4'
+.*Error: illegal operands `fdiv\.d a1,a2,a4,rne'
+.*Error: illegal operands `fdiv\.d a0,a1,a4'
+.*Error: illegal operands `fdiv\.d a0,a1,a4,rne'
+.*Error: illegal operands `fdiv\.d a0,a2,a1'
+.*Error: illegal operands `fdiv\.d a0,a2,a1,rne'
+.*Error: illegal operands `fsqrt\.d a1,a2'
+.*Error: illegal operands `fsqrt\.d a1,a2,rne'
+.*Error: illegal operands `fsqrt\.d a0,a1'
+.*Error: illegal operands `fsqrt\.d a0,a1,rne'
+.*Error: illegal operands `fmin\.d a1,a2,a4'
+.*Error: illegal operands `fmin\.d a0,a1,a4'
+.*Error: illegal operands `fmin\.d a0,a2,a1'
+.*Error: illegal operands `fmax\.d a1,a2,a4'
+.*Error: illegal operands `fmax\.d a0,a1,a4'
+.*Error: illegal operands `fmax\.d a0,a2,a1'
+.*Error: illegal operands `fmadd\.d a1,a2,a4,a6'
+.*Error: illegal operands `fmadd\.d a1,a2,a4,a6,rne'
+.*Error: illegal operands `fmadd\.d a0,a1,a4,a6'
+.*Error: illegal operands `fmadd\.d a0,a1,a4,a6,rne'
+.*Error: illegal operands `fmadd\.d a0,a2,a1,a6'
+.*Error: illegal operands `fmadd\.d a0,a2,a1,a6,rne'
+.*Error: illegal operands `fmadd\.d a0,a2,a4,a1'
+.*Error: illegal operands `fmadd\.d a0,a2,a4,a1,rne'
+.*Error: illegal operands `fnmadd\.d a1,a2,a4,a6'
+.*Error: illegal operands `fnmadd\.d a1,a2,a4,a6,rne'
+.*Error: illegal operands `fnmadd\.d a0,a1,a4,a6'
+.*Error: illegal operands `fnmadd\.d a0,a1,a4,a6,rne'
+.*Error: illegal operands `fnmadd\.d a0,a2,a1,a6'
+.*Error: illegal operands `fnmadd\.d a0,a2,a1,a6,rne'
+.*Error: illegal operands `fnmadd\.d a0,a2,a4,a1'
+.*Error: illegal operands `fnmadd\.d a0,a2,a4,a1,rne'
+.*Error: illegal operands `fmsub\.d a1,a2,a4,a6'
+.*Error: illegal operands `fmsub\.d a1,a2,a4,a6,rne'
+.*Error: illegal operands `fmsub\.d a0,a1,a4,a6'
+.*Error: illegal operands `fmsub\.d a0,a1,a4,a6,rne'
+.*Error: illegal operands `fmsub\.d a0,a2,a1,a6'
+.*Error: illegal operands `fmsub\.d a0,a2,a1,a6,rne'
+.*Error: illegal operands `fmsub\.d a0,a2,a4,a1'
+.*Error: illegal operands `fmsub\.d a0,a2,a4,a1,rne'
+.*Error: illegal operands `fnmsub\.d a1,a2,a4,a6'
+.*Error: illegal operands `fnmsub\.d a1,a2,a4,a6,rne'
+.*Error: illegal operands `fnmsub\.d a0,a1,a4,a6'
+.*Error: illegal operands `fnmsub\.d a0,a1,a4,a6,rne'
+.*Error: illegal operands `fnmsub\.d a0,a2,a1,a6'
+.*Error: illegal operands `fnmsub\.d a0,a2,a1,a6,rne'
+.*Error: illegal operands `fnmsub\.d a0,a2,a4,a1'
+.*Error: illegal operands `fnmsub\.d a0,a2,a4,a1,rne'
+.*Error: illegal operands `fsgnj\.d a1,a2,a4'
+.*Error: illegal operands `fsgnj\.d a0,a1,a4'
+.*Error: illegal operands `fsgnj\.d a0,a2,a1'
+.*Error: illegal operands `fsgnjn\.d a1,a2,a4'
+.*Error: illegal operands `fsgnjn\.d a0,a1,a4'
+.*Error: illegal operands `fsgnjn\.d a0,a2,a1'
+.*Error: illegal operands `fsgnjx\.d a1,a2,a4'
+.*Error: illegal operands `fsgnjx\.d a0,a1,a4'
+.*Error: illegal operands `fsgnjx\.d a0,a2,a1'
+.*Error: illegal operands `fmv\.d a1,a2'
+.*Error: illegal operands `fmv\.d a0,a1'
+.*Error: illegal operands `fneg\.d a1,a2'
+.*Error: illegal operands `fneg\.d a0,a1'
+.*Error: illegal operands `fabs\.d a1,a2'
+.*Error: illegal operands `fabs\.d a0,a1'
+.*Error: illegal operands `feq\.d a0,a1,a4'
+.*Error: illegal operands `feq\.d a0,a2,a1'
+.*Error: illegal operands `flt\.d a0,a1,a4'
+.*Error: illegal operands `flt\.d a0,a2,a1'
+.*Error: illegal operands `fle\.d a0,a1,a4'
+.*Error: illegal operands `fle\.d a0,a2,a1'
+.*Error: illegal operands `fgt\.d a0,a1,a4'
+.*Error: illegal operands `fgt\.d a0,a2,a1'
+.*Error: illegal operands `fge\.d a0,a1,a4'
+.*Error: illegal operands `fge\.d a0,a2,a1'
+.*Error: illegal operands `fclass\.d a0,a1'
+.*Error: illegal operands `fcvt\.w\.d a0,a1'
+.*Error: illegal operands `fcvt\.w\.d a0,a1,rne'
+.*Error: illegal operands `fcvt\.w\.d a3,a1'
+.*Error: illegal operands `fcvt\.w\.d a3,a1,rne'
+.*Error: illegal operands `fcvt\.wu\.d a0,a1'
+.*Error: illegal operands `fcvt\.wu\.d a0,a1,rne'
+.*Error: illegal operands `fcvt\.wu\.d a3,a1'
+.*Error: illegal operands `fcvt\.wu\.d a3,a1,rne'
+.*Error: illegal operands `fcvt\.d\.w a1,a2'
+.*Error: illegal operands `fcvt\.d\.w a1,a3'
+.*Error: illegal operands `fcvt\.d\.wu a1,a2'
+.*Error: illegal operands `fcvt\.d\.wu a1,a3'
+.*Error: illegal operands `fcvt\.s\.d a0,a1'
+.*Error: illegal operands `fcvt\.s\.d a0,a1,rne'
+.*Error: illegal operands `fcvt\.s\.d a3,a1'
+.*Error: illegal operands `fcvt\.s\.d a3,a1,rne'
+.*Error: illegal operands `fcvt\.d\.s a1,a2'
+.*Error: illegal operands `fcvt\.d\.s a1,a3'

gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s

@@ -0,0 +1,116 @@
+target:
+	fadd.d	a1, a2, a4
+	fadd.d	a1, a2, a4, rne
+	fadd.d	a0, a1, a4
+	fadd.d	a0, a1, a4, rne
+	fadd.d	a0, a2, a1
+	fadd.d	a0, a2, a1, rne
+	fsub.d	a1, a2, a4
+	fsub.d	a1, a2, a4, rne
+	fsub.d	a0, a1, a4
+	fsub.d	a0, a1, a4, rne
+	fsub.d	a0, a2, a1
+	fsub.d	a0, a2, a1, rne
+	fmul.d	a1, a2, a4
+	fmul.d	a1, a2, a4, rne
+	fmul.d	a0, a1, a4
+	fmul.d	a0, a1, a4, rne
+	fmul.d	a0, a2, a1
+	fmul.d	a0, a2, a1, rne
+	fdiv.d	a1, a2, a4
+	fdiv.d	a1, a2, a4, rne
+	fdiv.d	a0, a1, a4
+	fdiv.d	a0, a1, a4, rne
+	fdiv.d	a0, a2, a1
+	fdiv.d	a0, a2, a1, rne
+	fsqrt.d	a1, a2
+	fsqrt.d	a1, a2, rne
+	fsqrt.d	a0, a1
+	fsqrt.d	a0, a1, rne
+	fmin.d	a1, a2, a4
+	fmin.d	a0, a1, a4
+	fmin.d	a0, a2, a1
+	fmax.d	a1, a2, a4
+	fmax.d	a0, a1, a4
+	fmax.d	a0, a2, a1
+	fmadd.d	a1, a2, a4, a6
+	fmadd.d	a1, a2, a4, a6, rne
+	fmadd.d	a0, a1, a4, a6
+	fmadd.d	a0, a1, a4, a6, rne
+	fmadd.d	a0, a2, a1, a6
+	fmadd.d	a0, a2, a1, a6, rne
+	fmadd.d	a0, a2, a4, a1
+	fmadd.d	a0, a2, a4, a1, rne
+	fnmadd.d	a1, a2, a4, a6
+	fnmadd.d	a1, a2, a4, a6, rne
+	fnmadd.d	a0, a1, a4, a6
+	fnmadd.d	a0, a1, a4, a6, rne
+	fnmadd.d	a0, a2, a1, a6
+	fnmadd.d	a0, a2, a1, a6, rne
+	fnmadd.d	a0, a2, a4, a1
+	fnmadd.d	a0, a2, a4, a1, rne
+	fmsub.d	a1, a2, a4, a6
+	fmsub.d	a1, a2, a4, a6, rne
+	fmsub.d	a0, a1, a4, a6
+	fmsub.d	a0, a1, a4, a6, rne
+	fmsub.d	a0, a2, a1, a6
+	fmsub.d	a0, a2, a1, a6, rne
+	fmsub.d	a0, a2, a4, a1
+	fmsub.d	a0, a2, a4, a1, rne
+	fnmsub.d	a1, a2, a4, a6
+	fnmsub.d	a1, a2, a4, a6, rne
+	fnmsub.d	a0, a1, a4, a6
+	fnmsub.d	a0, a1, a4, a6, rne
+	fnmsub.d	a0, a2, a1, a6
+	fnmsub.d	a0, a2, a1, a6, rne
+	fnmsub.d	a0, a2, a4, a1
+	fnmsub.d	a0, a2, a4, a1, rne
+	fsgnj.d	a1, a2, a4
+	fsgnj.d	a0, a1, a4
+	fsgnj.d	a0, a2, a1
+	fsgnjn.d	a1, a2, a4
+	fsgnjn.d	a0, a1, a4
+	fsgnjn.d	a0, a2, a1
+	fsgnjx.d	a1, a2, a4
+	fsgnjx.d	a0, a1, a4
+	fsgnjx.d	a0, a2, a1
+	fmv.d	a1, a2
+	fmv.d	a0, a1
+	fneg.d	a1, a2
+	fneg.d	a0, a1
+	fabs.d	a1, a2
+	fabs.d	a0, a1
+	# Compare instructions: destination is a GPR
+	feq.d	a0, a1, a4
+	feq.d	a0, a2, a1
+	flt.d	a0, a1, a4
+	flt.d	a0, a2, a1
+	fle.d	a0, a1, a4
+	fle.d	a0, a2, a1
+	fgt.d	a0, a1, a4
+	fgt.d	a0, a2, a1
+	fge.d	a0, a1, a4
+	fge.d	a0, a2, a1
+	# fclass instruction: destination is a GPR
+	fclass.d	a0, a1
+	# fcvt instructions (float-int or int-float;
+	#                    integer operand register can be odd)
+	fcvt.w.d	a0, a1
+	fcvt.w.d	a0, a1, rne
+	fcvt.w.d	a3, a1
+	fcvt.w.d	a3, a1, rne
+	fcvt.wu.d	a0, a1
+	fcvt.wu.d	a0, a1, rne
+	fcvt.wu.d	a3, a1
+	fcvt.wu.d	a3, a1, rne
+	fcvt.d.w	a1, a2
+	fcvt.d.w	a1, a3
+	fcvt.d.wu	a1, a2
+	fcvt.d.wu	a1, a3
+	# fcvt instructions (float-float; FP32 operand can be odd)
+	fcvt.s.d	a0, a1
+	fcvt.s.d	a0, a1, rne
+	fcvt.s.d	a3, a1
+	fcvt.s.d	a3, a1, rne
+	fcvt.d.s	a1, a2
+	fcvt.d.s	a1, a3