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RISC-V: Better support for long instructions (assembler)
Commit bb99669 ("RISC-V/gas: allow generating up to 176-bit instructions with .insn") tried to start supporting long instructions but it was insufficient. 1. It heavily depended on the bignum internals (radix of 2^16), 2. It generates "value conflicts with instruction length" even if a big number instruction encoding does not exceed its expected length and 3. Because long opcode was handled separately (from struct riscv_cl_insn), some information like DWARF line number correspondence was missing. To resolve these problems, this commit: 1. Handles bignum (and its encodings) precisely and 2. Incorporates long opcode handling into regular instruction handling. This commit will be tested on the separate commit. gas/ChangeLog: * config/tc-riscv.c (struct riscv_cl_insn): Add long opcode field. (create_insn) Clear long opcode marker. (install_insn) Install longer opcode as well. (s_riscv_insn) Likewise. (riscv_ip_hardcode): Make big number handling stricter. Length and the value conflicts only if the bignum size exceeds the expected maximum length.
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