RISC-V: Reorganize disassembler state initialization

The current disassembler repeatedly checks current state per instruction:

-   Whether riscv_gpr_names is initialized to a non-NULL value
-   Whether the Zfinx extension is available
-   Whether the hash table is initialized

... but they are not frequently changed.

riscv_gpr_names is initialized to a non-NULL value when

-   The first disassembler option is specified, or
-   Not initialized with disassembler options
    (in the first print_insn_riscv function call).

We can safely initialize the default disassembler options prior to the
print_insn_riscv function call and this per-instruction checking of
riscv_gpr_names can be safely removed.

The opcode hash table initialization will be taken care with a later commit.

To group disassembler state initialization, this commit utilizes the
disassemble_init_for_target function.  As a side effect, this will also fix
a potential issue when disassembler options is set and then unset on GDB.
This idea is based on opcodes/ppc-dis.c and opcodes/wasm32-dis.c.

New callback function init_riscv_dis_state_for_arch_and_options is called
when either the architecture string or an option is possibly changed.

We can now group the disassembler state initialization together.
It makes state initialization clearer and makes further changes easier.

In performance perspective, this commit has various effects (-5% to 6%).
However, this commit makes implementing large optimizations easier
as well as "RISC-V: Split match/print steps on disassembler".

include/ChangeLog:

	* dis-asm.h (disassemble_init_riscv): Add declaration of
	disassemble_init_riscv.

opcodes/ChangeLog:

	* disassemble.c (disassemble_init_for_target): Call
	disassemble_init_riscv to group state initialization together.
	* riscv-dis.c
	(xlen_by_mach, xlen_by_elf): New variables to store
	environment-inferred XLEN.
	(is_numeric): New.  Instead of directly setting
	riscv_{gpr,fpr}_names, use this to store an option.
	(update_riscv_dis_xlen): New function to set actual XLEN from
	xlen_by_mach and xlen_by_elf variables.
	(init_riscv_dis_state_for_arch_and_options): New callback function
	called when either the architecture or an option is changed.  Set
	riscv_{gpr,fpr}_names here.
	(set_default_riscv_dis_options): Initialize is_numeric instead of
	riscv_gpr_names and riscv_fpr_names.
	(parse_riscv_dis_option_without_args): When the "numeric" option
	is specified, write to is_numeric instead of register names.
	(parse_riscv_dis_options): Suppress setting the default options
	here and let disassemble_init_riscv to initialize them.
	(riscv_disassemble_insn): Move probing Zfinx and setting XLEN
	portions to init_riscv_dis_state_for_arch_and_options and
	update_riscv_dis_xlen.
	(riscv_get_map_state): If a mapping symbol with ISA string is
	suitable, call init_riscv_dis_state_for_arch_and_options function
	to update disassembler state.
	(print_insn_riscv): Update XLEN only if we haven't guessed correct
	XLEN for the disassembler.  Stop checking disassembler options for
	every instruction and let disassemble_init_riscv to parse options.
	(riscv_get_disassembler): Call
	init_riscv_dis_state_for_arch_and_options because the architecture
	string is possibly updated here.
	(disassemble_init_riscv): New function to initialize the
	structure, reset/guess correct XLEN and reset/parse disassembler
	options.

include/dis-asm.h

@@ -394,6 +394,7 @@ extern bool arm_symbol_is_valid (asymbol *, struct disassemble_info *);
 extern bool csky_symbol_is_valid (asymbol *, struct disassemble_info *);
 extern bool riscv_symbol_is_valid (asymbol *, struct disassemble_info *);
 extern void disassemble_init_powerpc (struct disassemble_info *);
+extern void disassemble_init_riscv (struct disassemble_info *);
 extern void disassemble_init_s390 (struct disassemble_info *);
 extern void disassemble_init_wasm32 (struct disassemble_info *);
 extern void disassemble_init_nds32 (struct disassemble_info *);

opcodes/disassemble.c

@@ -701,7 +701,7 @@ disassemble_init_for_target (struct disassemble_info * info)
 #endif
 #ifdef ARCH_riscv
     case bfd_arch_riscv:
-      info->symbol_is_valid = riscv_symbol_is_valid;
+      disassemble_init_riscv (info);
       info->created_styled_output = true;
       break;
 #endif

opcodes/riscv-dis.c

@@ -35,6 +35,12 @@
 /* Current XLEN for the disassembler.  */
 static unsigned xlen = 0;
 
+/* XLEN as inferred by the machine architecture.  */
+static unsigned xlen_by_mach = 0;
+
+/* XLEN as inferred by ELF header.  */
+static unsigned xlen_by_elf = 0;
+
 /* Default ISA specification version (constant as of now).  */
 static enum riscv_spec_class default_isa_spec = ISA_SPEC_CLASS_DRAFT - 1;
 
@@ -75,16 +81,57 @@ static const char * const *riscv_fpr_names;
 
 /* If set, disassemble as most general instruction.  */
 static bool no_aliases = false;
+
+/* If set, disassemble with numeric register names.  */
+static bool is_numeric = false;
+
+
+/* Guess and update current XLEN.  */
+
+static void
+update_riscv_dis_xlen (struct disassemble_info *info)
+{
+  /* Set XLEN with following precedence rules:
+     1. BFD machine architecture set by either:
+       a. -m riscv:rv[32|64] option (GDB: set arch riscv:rv[32|64])
+       b. ELF class in actual ELF header (only on RISC-V ELF)
+       This is only effective if XLEN-specific BFD machine architecture is
+       chosen.  If XLEN-neutral (like riscv), BFD machine architecture is
+       ignored on XLEN selection.
+     2. ELF class in dummy ELF header.  */
+  if (xlen_by_mach != 0)
+    xlen = xlen_by_mach;
+  else if (xlen_by_elf != 0)
+    xlen = xlen_by_elf;
+  else if (info != NULL && info->section != NULL)
+    {
+      Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner);
+      xlen = xlen_by_elf = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32;
+    }
+}
+
+/* Initialization (for arch and options).  */
+
+static void
+init_riscv_dis_state_for_arch_and_options (void)
+{
+  /* Set GPR register names to disassemble.  */
+  riscv_gpr_names = is_numeric ? riscv_gpr_names_numeric : riscv_gpr_names_abi;
+  /* Set FPR register names to disassemble.  */
+  riscv_fpr_names
+      = !riscv_subset_supports (&riscv_rps_dis, "zfinx")
+	    ? (is_numeric ? riscv_fpr_names_numeric : riscv_fpr_names_abi)
+	    : riscv_gpr_names;
+}
 
 
 /* Set default RISC-V disassembler options.  */
 
 static void
 set_default_riscv_dis_options (void)
 {
-  riscv_gpr_names = riscv_gpr_names_abi;
-  riscv_fpr_names = riscv_fpr_names_abi;
   no_aliases = false;
+  is_numeric = false;
 }
 
 /* Parse RISC-V disassembler option (without arguments).  */
@@ -95,10 +142,7 @@ parse_riscv_dis_option_without_args (const char *option)
   if (strcmp (option, "no-aliases") == 0)
     no_aliases = true;
   else if (strcmp (option, "numeric") == 0)
-    {
-      riscv_gpr_names = riscv_gpr_names_numeric;
-      riscv_fpr_names = riscv_fpr_names_numeric;
-    }
+    is_numeric = true;
   else
     return false;
   return true;
@@ -166,8 +210,6 @@ parse_riscv_dis_options (const char *opts_in)
 {
   char *opts = xstrdup (opts_in), *opt = opts, *opt_end = opts;
 
-  set_default_riscv_dis_options ();
-
   for ( ; opt_end != NULL; opt = opt_end + 1)
     {
       if ((opt_end = strchr (opt, ',')) != NULL)
@@ -740,25 +782,6 @@ riscv_disassemble_insn (bfd_vma memaddr,
   matched_op = NULL;
   op = riscv_hash[OP_HASH_IDX (word)];
 
-  /* If XLEN is not known, get its value from the ELF class.  */
-  if (info->mach == bfd_mach_riscv64)
-    xlen = 64;
-  else if (info->mach == bfd_mach_riscv32)
-    xlen = 32;
-  else if (info->section != NULL)
-    {
-      Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner);
-      xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32;
-    }
-
-  /* If arch has the Zfinx extension, replace FPR with GPR.  */
-  if (riscv_subset_supports (&riscv_rps_dis, "zfinx"))
-    riscv_fpr_names = riscv_gpr_names;
-  else
-    riscv_fpr_names = riscv_gpr_names == riscv_gpr_names_abi
-			  ? riscv_fpr_names_abi
-			  : riscv_fpr_names_numeric;
-
   for (; op && op->name; op++)
     {
       /* Does the opcode match?  */
@@ -892,6 +915,7 @@ riscv_get_map_state (int n,
     {
       riscv_release_subset_list (&riscv_subsets);
       riscv_parse_subset (&riscv_rps_dis, arch);
+      init_riscv_dis_state_for_arch_and_options ();
     }
   return true;
 }
@@ -1156,14 +1180,9 @@ print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info)
   int (*riscv_disassembler) (bfd_vma, insn_t, const bfd_byte *,
 			     struct disassemble_info *);
 
-  if (info->disassembler_options != NULL)
-    {
-      parse_riscv_dis_options (info->disassembler_options);
-      /* Avoid repeatedly parsing the options.  */
-      info->disassembler_options = NULL;
-    }
-  else if (riscv_gpr_names == NULL)
-    set_default_riscv_dis_options ();
+  /* Guess and update XLEN if we haven't determined it yet.  */
+  if (xlen == 0)
+    update_riscv_dis_xlen (info);
 
   if (info->private_data == NULL && !riscv_init_disasm_info (info))
     return -1;
@@ -1230,9 +1249,32 @@ riscv_get_disassembler (bfd *abfd)
 
   riscv_release_subset_list (&riscv_subsets);
   riscv_parse_subset (&riscv_rps_dis, default_arch);
+  init_riscv_dis_state_for_arch_and_options ();
   return print_insn_riscv;
 }
 
+/* Initialize disassemble_info and parse options.  */
+
+void
+disassemble_init_riscv (struct disassemble_info *info)
+{
+  info->symbol_is_valid = riscv_symbol_is_valid;
+  /* Clear previous XLEN and guess by mach.  */
+  xlen = 0;
+  xlen_by_mach = 0;
+  xlen_by_elf = 0;
+  if (info->mach == bfd_mach_riscv64)
+    xlen_by_mach = 64;
+  else if (info->mach == bfd_mach_riscv32)
+    xlen_by_mach = 32;
+  update_riscv_dis_xlen (info);
+  /* Parse disassembler options.  */
+  set_default_riscv_dis_options ();
+  if (info->disassembler_options != NULL)
+    parse_riscv_dis_options (info->disassembler_options);
+  init_riscv_dis_state_for_arch_and_options ();
+}
+
 /* Prevent use of the fake labels that are generated as part of the DWARF
    and for relaxable relocations in the assembler.  */