RISC-V: Add disassembler arch option tests

This commit adds certain tests for arch=ARCH disassembler option
(to override ISA and extensions).

gas/ChangeLog:

	* testsuite/gas/riscv/dis-arch-override.s: New test.
	* testsuite/gas/riscv/dis-arch-override-1.d: Likewise.
	* testsuite/gas/riscv/dis-arch-override-2.d: Likewise.
	* testsuite/gas/riscv/dis-arch-override-3.d: Likewise.

gas/testsuite/gas/riscv/dis-arch-override-1.d

@@ -0,0 +1,13 @@
+#as: -march=rv64imfd_zbb
+#source: dis-arch-override.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+00c5f053[ 	]+fadd.s[ 	]+ft0,fa1,fa2
+[ 	]+[0-9a-f]+:[ 	]+02c5f053[ 	]+fadd.d[ 	]+ft0,fa1,fa2
+[ 	]+[0-9a-f]+:[ 	]+30102573[ 	]+csrr[ 	]+a0,misa
+[ 	]+[0-9a-f]+:[ 	]+0805c53b[ 	]+zext.h[ 	]+a0,a1

gas/testsuite/gas/riscv/dis-arch-override-2.d

@@ -0,0 +1,13 @@
+#as: -march=rv64imfd_zbb
+#source: dis-arch-override.s
+#objdump: -d -M arch=rv32im_zfinx_zbkb
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+00c5f053[ 	]+fadd.s[ 	]+zero,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5f053[ 	]+\.4byte[ 	]+0x2c5f053
+[ 	]+[0-9a-f]+:[ 	]+30102573[ 	]+csrr[ 	]+a0,misa
+[ 	]+[0-9a-f]+:[ 	]+0805c53b[ 	]+packw[ 	]+a0,a1,zero

gas/testsuite/gas/riscv/dis-arch-override-3.d

@@ -0,0 +1,13 @@
+#as: -march=rv64imfd_zbb
+#source: dis-arch-override.s
+#objdump: -d -m riscv -M arch=rv32im_zfinx_zbkb
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+00c5f053[ 	]+fadd.s[ 	]+zero,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5f053[ 	]+\.4byte[ 	]+0x2c5f053
+[ 	]+[0-9a-f]+:[ 	]+30102573[ 	]+csrr[ 	]+a0,misa
+[ 	]+[0-9a-f]+:[ 	]+0805c53b[ 	]+\.4byte[ 	]+0x805c53b

gas/testsuite/gas/riscv/dis-arch-override.s

@@ -0,0 +1,45 @@
+# Assembler configuration:
+#    -march=rv64imfd_zbb
+# Disassembler configurations:
+#    Test 1: -d
+#    Test 2: -d -M arch=rv32im_zfinx_zbkb
+#    Test 3: -d -m riscv -M arch=rv32im_zfinx_zbkb
+
+target:
+	# Assembler               : fadd.s (F)
+	# Disassembler (test 2/3) : fadd.s (Zfinx)
+	# Test that all three operands point to GPRs.
+	fadd.s	ft0, fa1, fa2
+
+	# Assembler               : fadd.d (D)
+	# Disassembler (test 2/3) : (invalid)
+	# On disassembler option on test 2, Zdinx is not present.  So,
+	# it should be disassembled as an invalid instruction.
+	fadd.d	ft0, fa1, fa2
+
+	# Assembler               : csrr (Zicsr)
+	# Disassembler (test 2/3) : csrr (Zicsr)
+	# When assembling, Zicsr is implied by F.  When disassembling,
+	# Zicsr is implied by Zfinx.  On both cases, csrr should be
+	# disassembled as csrr.
+	csrr	a0, misa
+
+	# Assembler               : zext.h (Zbb)
+	# Disassembler (test 2)   : packw  (Zbkb)
+	# Disassembler (test 3)   : (invalid)
+	# Since zext.h specialized instruction does not exist in Zbkb
+	# and we disassemble the output with Zbkb, this instruction
+	# should be disassembled as a packw instruction (on RV64).
+	#
+	# We specify -M arch=rv32im_zfinx_zbkb on disassembling on test
+	# 2 and 3.  But, XLEN part of the ISA string is effective
+	# only if XLEN-neutral machine is specified by `-m riscv' option
+	# (because we are disassembling 64-bit RISC-V ELF file, BFD
+	# architecture is set to `riscv:rv64' unless `-m' option
+	# is specified).
+	#
+	# As a result, test 3 (with `-m riscv' option) disassembles with
+	# RV32 but test 2 (without it) does with RV64.
+	# It changes the result of disassembling since packw instruction
+	# is invalid on RV32.
+	zext.h	a0, a1