RISC-V: Add testcases for Z[dq]inx register pairs

This commit adds several assembler/disassembler tests for Zdinx/Zqinx
register pairs.  They make sure that we don't assemble/disassemble
invalid encodings.

gas/ChangeLog:

	* testsuite/gas/riscv/zdinx-32-regpair.s: Test RV32_Zdinx
	register pairs.
	* testsuite/gas/riscv/zdinx-32-regpair.d: Likewise.
	* testsuite/gas/riscv/zdinx-32-regpair-dis.s: New test to make
	sure that invalid encoding is not disassembled.
	* testsuite/gas/riscv/zdinx-32-regpair-dis.d: Likewise.
	* testsuite/gas/riscv/zdinx-32-regpair-fail.s: Test RV32_Zdinx
	register pairs (failure cases).
	* testsuite/gas/riscv/zdinx-32-regpair-fail.d: Likewise.
	* testsuite/gas/riscv/zdinx-32-regpair-fail.l: Likewise.
	* testsuite/gas/riscv/zqinx-64-regpair.s: Test RV64_Zqinx
	register pairs.
	* testsuite/gas/riscv/zqinx-64-regpair.d: Likewise.
	* testsuite/gas/riscv/zqinx-32-regpair-dis.s: New test to make
	sure that invalid encodings are not disassembled.
	* testsuite/gas/riscv/zqinx-32-regpair-dis.d: Likewise.
	* testsuite/gas/riscv/zqinx-64-regpair-dis.s: New test to make
	sure that invalid encoding is not disassembled.
	* testsuite/gas/riscv/zqinx-64-regpair-dis.d: Likewise.
	* testsuite/gas/riscv/zqinx-64-regpair-fail.s: Test RV64_Zqinx
	register pairs (failure cases).
	* testsuite/gas/riscv/zqinx-64-regpair-fail.d: Likewise.
	* testsuite/gas/riscv/zqinx-64-regpair-fail.l: Likewise.
	* testsuite/gas/riscv/zqinx-32-regpair.s: Test RV32_Zqinx
	register pairs and quad-register groups.
	* testsuite/gas/riscv/zqinx-32-regpair.d: Likewise.
	* testsuite/gas/riscv/zqinx-32-regpair-fail.s: Test RV32_Zqinx
	register pairs and quad-register groups (failure cases).
	* testsuite/gas/riscv/zqinx-32-regpair-fail.d: Likewise.
	* testsuite/gas/riscv/zqinx-32-regpair-fail.l: Likewise.

gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d

@@ -0,0 +1,11 @@
+#as: -march=rv32ima_zdinx
+#source: zdinx-32-regpair-dis.s
+#objdump: -dr -Mnumeric
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+02627153[ 	]+fadd.d[ 	]+x2,x4,x6
+[ 	]+[0-9a-f]+:[ 	]+0272f1d3[ 	]+\.4byte[ 	]+0x272f1d3

gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s

@@ -0,0 +1,5 @@
+target:
+	# fadd.d x2, x4, x6
+	.insn r	OP_FP, 0x7, 0x01, x2, x4, x6
+	# fadd.d x3, x5, x7 (invalid)
+	.insn r	OP_FP, 0x7, 0x01, x3, x5, x7

gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d

@@ -0,0 +1,3 @@
+#as: -march=rv32ima_zdinx
+#source: zdinx-32-regpair-fail.s
+#error_output: zdinx-32-regpair-fail.l

gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l

@@ -0,0 +1,111 @@
+.*Assembler messages:
+.*Error: illegal operands `fadd\.d a1,a2,a4'
+.*Error: illegal operands `fadd\.d a1,a2,a4,rne'
+.*Error: illegal operands `fadd\.d a0,a1,a4'
+.*Error: illegal operands `fadd\.d a0,a1,a4,rne'
+.*Error: illegal operands `fadd\.d a0,a2,a1'
+.*Error: illegal operands `fadd\.d a0,a2,a1,rne'
+.*Error: illegal operands `fsub\.d a1,a2,a4'
+.*Error: illegal operands `fsub\.d a1,a2,a4,rne'
+.*Error: illegal operands `fsub\.d a0,a1,a4'
+.*Error: illegal operands `fsub\.d a0,a1,a4,rne'
+.*Error: illegal operands `fsub\.d a0,a2,a1'
+.*Error: illegal operands `fsub\.d a0,a2,a1,rne'
+.*Error: illegal operands `fmul\.d a1,a2,a4'
+.*Error: illegal operands `fmul\.d a1,a2,a4,rne'
+.*Error: illegal operands `fmul\.d a0,a1,a4'
+.*Error: illegal operands `fmul\.d a0,a1,a4,rne'
+.*Error: illegal operands `fmul\.d a0,a2,a1'
+.*Error: illegal operands `fmul\.d a0,a2,a1,rne'
+.*Error: illegal operands `fdiv\.d a1,a2,a4'
+.*Error: illegal operands `fdiv\.d a1,a2,a4,rne'
+.*Error: illegal operands `fdiv\.d a0,a1,a4'
+.*Error: illegal operands `fdiv\.d a0,a1,a4,rne'
+.*Error: illegal operands `fdiv\.d a0,a2,a1'
+.*Error: illegal operands `fdiv\.d a0,a2,a1,rne'
+.*Error: illegal operands `fsqrt\.d a1,a2'
+.*Error: illegal operands `fsqrt\.d a1,a2,rne'
+.*Error: illegal operands `fsqrt\.d a0,a1'
+.*Error: illegal operands `fsqrt\.d a0,a1,rne'
+.*Error: illegal operands `fmin\.d a1,a2,a4'
+.*Error: illegal operands `fmin\.d a0,a1,a4'
+.*Error: illegal operands `fmin\.d a0,a2,a1'
+.*Error: illegal operands `fmax\.d a1,a2,a4'
+.*Error: illegal operands `fmax\.d a0,a1,a4'
+.*Error: illegal operands `fmax\.d a0,a2,a1'
+.*Error: illegal operands `fmadd\.d a1,a2,a4,a6'
+.*Error: illegal operands `fmadd\.d a1,a2,a4,a6,rne'
+.*Error: illegal operands `fmadd\.d a0,a1,a4,a6'
+.*Error: illegal operands `fmadd\.d a0,a1,a4,a6,rne'
+.*Error: illegal operands `fmadd\.d a0,a2,a1,a6'
+.*Error: illegal operands `fmadd\.d a0,a2,a1,a6,rne'
+.*Error: illegal operands `fmadd\.d a0,a2,a4,a1'
+.*Error: illegal operands `fmadd\.d a0,a2,a4,a1,rne'
+.*Error: illegal operands `fnmadd\.d a1,a2,a4,a6'
+.*Error: illegal operands `fnmadd\.d a1,a2,a4,a6,rne'
+.*Error: illegal operands `fnmadd\.d a0,a1,a4,a6'
+.*Error: illegal operands `fnmadd\.d a0,a1,a4,a6,rne'
+.*Error: illegal operands `fnmadd\.d a0,a2,a1,a6'
+.*Error: illegal operands `fnmadd\.d a0,a2,a1,a6,rne'
+.*Error: illegal operands `fnmadd\.d a0,a2,a4,a1'
+.*Error: illegal operands `fnmadd\.d a0,a2,a4,a1,rne'
+.*Error: illegal operands `fmsub\.d a1,a2,a4,a6'
+.*Error: illegal operands `fmsub\.d a1,a2,a4,a6,rne'
+.*Error: illegal operands `fmsub\.d a0,a1,a4,a6'
+.*Error: illegal operands `fmsub\.d a0,a1,a4,a6,rne'
+.*Error: illegal operands `fmsub\.d a0,a2,a1,a6'
+.*Error: illegal operands `fmsub\.d a0,a2,a1,a6,rne'
+.*Error: illegal operands `fmsub\.d a0,a2,a4,a1'
+.*Error: illegal operands `fmsub\.d a0,a2,a4,a1,rne'
+.*Error: illegal operands `fnmsub\.d a1,a2,a4,a6'
+.*Error: illegal operands `fnmsub\.d a1,a2,a4,a6,rne'
+.*Error: illegal operands `fnmsub\.d a0,a1,a4,a6'
+.*Error: illegal operands `fnmsub\.d a0,a1,a4,a6,rne'
+.*Error: illegal operands `fnmsub\.d a0,a2,a1,a6'
+.*Error: illegal operands `fnmsub\.d a0,a2,a1,a6,rne'
+.*Error: illegal operands `fnmsub\.d a0,a2,a4,a1'
+.*Error: illegal operands `fnmsub\.d a0,a2,a4,a1,rne'
+.*Error: illegal operands `fsgnj\.d a1,a2,a4'
+.*Error: illegal operands `fsgnj\.d a0,a1,a4'
+.*Error: illegal operands `fsgnj\.d a0,a2,a1'
+.*Error: illegal operands `fsgnjn\.d a1,a2,a4'
+.*Error: illegal operands `fsgnjn\.d a0,a1,a4'
+.*Error: illegal operands `fsgnjn\.d a0,a2,a1'
+.*Error: illegal operands `fsgnjx\.d a1,a2,a4'
+.*Error: illegal operands `fsgnjx\.d a0,a1,a4'
+.*Error: illegal operands `fsgnjx\.d a0,a2,a1'
+.*Error: illegal operands `fmv\.d a1,a2'
+.*Error: illegal operands `fmv\.d a0,a1'
+.*Error: illegal operands `fneg\.d a1,a2'
+.*Error: illegal operands `fneg\.d a0,a1'
+.*Error: illegal operands `fabs\.d a1,a2'
+.*Error: illegal operands `fabs\.d a0,a1'
+.*Error: illegal operands `feq\.d a0,a1,a4'
+.*Error: illegal operands `feq\.d a0,a2,a1'
+.*Error: illegal operands `flt\.d a0,a1,a4'
+.*Error: illegal operands `flt\.d a0,a2,a1'
+.*Error: illegal operands `fle\.d a0,a1,a4'
+.*Error: illegal operands `fle\.d a0,a2,a1'
+.*Error: illegal operands `fgt\.d a0,a1,a4'
+.*Error: illegal operands `fgt\.d a0,a2,a1'
+.*Error: illegal operands `fge\.d a0,a1,a4'
+.*Error: illegal operands `fge\.d a0,a2,a1'
+.*Error: illegal operands `fclass\.d a0,a1'
+.*Error: illegal operands `fcvt\.w\.d a0,a1'
+.*Error: illegal operands `fcvt\.w\.d a0,a1,rne'
+.*Error: illegal operands `fcvt\.w\.d a3,a1'
+.*Error: illegal operands `fcvt\.w\.d a3,a1,rne'
+.*Error: illegal operands `fcvt\.wu\.d a0,a1'
+.*Error: illegal operands `fcvt\.wu\.d a0,a1,rne'
+.*Error: illegal operands `fcvt\.wu\.d a3,a1'
+.*Error: illegal operands `fcvt\.wu\.d a3,a1,rne'
+.*Error: illegal operands `fcvt\.d\.w a1,a2'
+.*Error: illegal operands `fcvt\.d\.w a1,a3'
+.*Error: illegal operands `fcvt\.d\.wu a1,a2'
+.*Error: illegal operands `fcvt\.d\.wu a1,a3'
+.*Error: illegal operands `fcvt\.s\.d a0,a1'
+.*Error: illegal operands `fcvt\.s\.d a0,a1,rne'
+.*Error: illegal operands `fcvt\.s\.d a3,a1'
+.*Error: illegal operands `fcvt\.s\.d a3,a1,rne'
+.*Error: illegal operands `fcvt\.d\.s a1,a2'
+.*Error: illegal operands `fcvt\.d\.s a1,a3'

gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s

@@ -0,0 +1,116 @@
+target:
+	fadd.d	a1, a2, a4
+	fadd.d	a1, a2, a4, rne
+	fadd.d	a0, a1, a4
+	fadd.d	a0, a1, a4, rne
+	fadd.d	a0, a2, a1
+	fadd.d	a0, a2, a1, rne
+	fsub.d	a1, a2, a4
+	fsub.d	a1, a2, a4, rne
+	fsub.d	a0, a1, a4
+	fsub.d	a0, a1, a4, rne
+	fsub.d	a0, a2, a1
+	fsub.d	a0, a2, a1, rne
+	fmul.d	a1, a2, a4
+	fmul.d	a1, a2, a4, rne
+	fmul.d	a0, a1, a4
+	fmul.d	a0, a1, a4, rne
+	fmul.d	a0, a2, a1
+	fmul.d	a0, a2, a1, rne
+	fdiv.d	a1, a2, a4
+	fdiv.d	a1, a2, a4, rne
+	fdiv.d	a0, a1, a4
+	fdiv.d	a0, a1, a4, rne
+	fdiv.d	a0, a2, a1
+	fdiv.d	a0, a2, a1, rne
+	fsqrt.d	a1, a2
+	fsqrt.d	a1, a2, rne
+	fsqrt.d	a0, a1
+	fsqrt.d	a0, a1, rne
+	fmin.d	a1, a2, a4
+	fmin.d	a0, a1, a4
+	fmin.d	a0, a2, a1
+	fmax.d	a1, a2, a4
+	fmax.d	a0, a1, a4
+	fmax.d	a0, a2, a1
+	fmadd.d	a1, a2, a4, a6
+	fmadd.d	a1, a2, a4, a6, rne
+	fmadd.d	a0, a1, a4, a6
+	fmadd.d	a0, a1, a4, a6, rne
+	fmadd.d	a0, a2, a1, a6
+	fmadd.d	a0, a2, a1, a6, rne
+	fmadd.d	a0, a2, a4, a1
+	fmadd.d	a0, a2, a4, a1, rne
+	fnmadd.d	a1, a2, a4, a6
+	fnmadd.d	a1, a2, a4, a6, rne
+	fnmadd.d	a0, a1, a4, a6
+	fnmadd.d	a0, a1, a4, a6, rne
+	fnmadd.d	a0, a2, a1, a6
+	fnmadd.d	a0, a2, a1, a6, rne
+	fnmadd.d	a0, a2, a4, a1
+	fnmadd.d	a0, a2, a4, a1, rne
+	fmsub.d	a1, a2, a4, a6
+	fmsub.d	a1, a2, a4, a6, rne
+	fmsub.d	a0, a1, a4, a6
+	fmsub.d	a0, a1, a4, a6, rne
+	fmsub.d	a0, a2, a1, a6
+	fmsub.d	a0, a2, a1, a6, rne
+	fmsub.d	a0, a2, a4, a1
+	fmsub.d	a0, a2, a4, a1, rne
+	fnmsub.d	a1, a2, a4, a6
+	fnmsub.d	a1, a2, a4, a6, rne
+	fnmsub.d	a0, a1, a4, a6
+	fnmsub.d	a0, a1, a4, a6, rne
+	fnmsub.d	a0, a2, a1, a6
+	fnmsub.d	a0, a2, a1, a6, rne
+	fnmsub.d	a0, a2, a4, a1
+	fnmsub.d	a0, a2, a4, a1, rne
+	fsgnj.d	a1, a2, a4
+	fsgnj.d	a0, a1, a4
+	fsgnj.d	a0, a2, a1
+	fsgnjn.d	a1, a2, a4
+	fsgnjn.d	a0, a1, a4
+	fsgnjn.d	a0, a2, a1
+	fsgnjx.d	a1, a2, a4
+	fsgnjx.d	a0, a1, a4
+	fsgnjx.d	a0, a2, a1
+	fmv.d	a1, a2
+	fmv.d	a0, a1
+	fneg.d	a1, a2
+	fneg.d	a0, a1
+	fabs.d	a1, a2
+	fabs.d	a0, a1
+	# Compare instructions: destination is a GPR
+	feq.d	a0, a1, a4
+	feq.d	a0, a2, a1
+	flt.d	a0, a1, a4
+	flt.d	a0, a2, a1
+	fle.d	a0, a1, a4
+	fle.d	a0, a2, a1
+	fgt.d	a0, a1, a4
+	fgt.d	a0, a2, a1
+	fge.d	a0, a1, a4
+	fge.d	a0, a2, a1
+	# fclass instruction: destination is a GPR
+	fclass.d	a0, a1
+	# fcvt instructions (float-int or int-float;
+	#                    integer operand register can be odd)
+	fcvt.w.d	a0, a1
+	fcvt.w.d	a0, a1, rne
+	fcvt.w.d	a3, a1
+	fcvt.w.d	a3, a1, rne
+	fcvt.wu.d	a0, a1
+	fcvt.wu.d	a0, a1, rne
+	fcvt.wu.d	a3, a1
+	fcvt.wu.d	a3, a1, rne
+	fcvt.d.w	a1, a2
+	fcvt.d.w	a1, a3
+	fcvt.d.wu	a1, a2
+	fcvt.d.wu	a1, a3
+	# fcvt instructions (float-float; FP32 operand can be odd)
+	fcvt.s.d	a0, a1
+	fcvt.s.d	a0, a1, rne
+	fcvt.s.d	a3, a1
+	fcvt.s.d	a3, a1, rne
+	fcvt.d.s	a1, a2
+	fcvt.d.s	a1, a3

gas/testsuite/gas/riscv/zdinx-32-regpair.d

@@ -0,0 +1,65 @@
+#as: -march=rv32ima_zdinx
+#source: zdinx-32-regpair.s
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+02e67553[ 	]+fadd.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+02e60553[ 	]+fadd.d[ 	]+a0,a2,a4,rne
+[ 	]+[0-9a-f]+:[ 	]+0ae67553[ 	]+fsub.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+0ae60553[ 	]+fsub.d[ 	]+a0,a2,a4,rne
+[ 	]+[0-9a-f]+:[ 	]+12e67553[ 	]+fmul.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+12e60553[ 	]+fmul.d[ 	]+a0,a2,a4,rne
+[ 	]+[0-9a-f]+:[ 	]+1ae67553[ 	]+fdiv.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+1ae60553[ 	]+fdiv.d[ 	]+a0,a2,a4,rne
+[ 	]+[0-9a-f]+:[ 	]+5a067553[ 	]+fsqrt.d[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+5a060553[ 	]+fsqrt.d[ 	]+a0,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+2ae60553[ 	]+fmin.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+2ae61553[ 	]+fmax.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+82e67543[ 	]+fmadd.d[ 	]+a0,a2,a4,a6
+[ 	]+[0-9a-f]+:[ 	]+82e60543[ 	]+fmadd.d[ 	]+a0,a2,a4,a6,rne
+[ 	]+[0-9a-f]+:[ 	]+82e6754f[ 	]+fnmadd.d[ 	]+a0,a2,a4,a6
+[ 	]+[0-9a-f]+:[ 	]+82e6054f[ 	]+fnmadd.d[ 	]+a0,a2,a4,a6,rne
+[ 	]+[0-9a-f]+:[ 	]+82e67547[ 	]+fmsub.d[ 	]+a0,a2,a4,a6
+[ 	]+[0-9a-f]+:[ 	]+82e60547[ 	]+fmsub.d[ 	]+a0,a2,a4,a6,rne
+[ 	]+[0-9a-f]+:[ 	]+82e6754b[ 	]+fnmsub.d[ 	]+a0,a2,a4,a6
+[ 	]+[0-9a-f]+:[ 	]+82e6054b[ 	]+fnmsub.d[ 	]+a0,a2,a4,a6,rne
+[ 	]+[0-9a-f]+:[ 	]+22e60553[ 	]+fsgnj.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+22e61553[ 	]+fsgnjn.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+22e62553[ 	]+fsgnjx.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+22c60553[ 	]+fmv.d[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+22c61553[ 	]+fneg.d[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+22c62553[ 	]+fabs.d[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+a2e62553[ 	]+feq.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+a2e625d3[ 	]+feq.d[ 	]+a1,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+a2e61553[ 	]+flt.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+a2e615d3[ 	]+flt.d[ 	]+a1,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+a2e60553[ 	]+fle.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+a2e605d3[ 	]+fle.d[ 	]+a1,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+a2c71553[ 	]+flt.d[ 	]+a0,a4,a2
+[ 	]+[0-9a-f]+:[ 	]+a2c715d3[ 	]+flt.d[ 	]+a1,a4,a2
+[ 	]+[0-9a-f]+:[ 	]+a2c70553[ 	]+fle.d[ 	]+a0,a4,a2
+[ 	]+[0-9a-f]+:[ 	]+a2c705d3[ 	]+fle.d[ 	]+a1,a4,a2
+[ 	]+[0-9a-f]+:[ 	]+e2061553[ 	]+fclass.d[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+e20615d3[ 	]+fclass.d[ 	]+a1,a2
+[ 	]+[0-9a-f]+:[ 	]+c2067553[ 	]+fcvt.w.d[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+c2060553[ 	]+fcvt.w.d[ 	]+a0,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+c20675d3[ 	]+fcvt.w.d[ 	]+a1,a2
+[ 	]+[0-9a-f]+:[ 	]+c20605d3[ 	]+fcvt.w.d[ 	]+a1,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+c2167553[ 	]+fcvt.wu.d[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+c2160553[ 	]+fcvt.wu.d[ 	]+a0,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+c21675d3[ 	]+fcvt.wu.d[ 	]+a1,a2
+[ 	]+[0-9a-f]+:[ 	]+c21605d3[ 	]+fcvt.wu.d[ 	]+a1,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+d2060553[ 	]+fcvt.d.w[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+d2058553[ 	]+fcvt.d.w[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+d2160553[ 	]+fcvt.d.wu[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+d2158553[ 	]+fcvt.d.wu[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+40167553[ 	]+fcvt.s.d[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+40160553[ 	]+fcvt.s.d[ 	]+a0,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+401675d3[ 	]+fcvt.s.d[ 	]+a1,a2
+[ 	]+[0-9a-f]+:[ 	]+401605d3[ 	]+fcvt.s.d[ 	]+a1,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+42060553[ 	]+fcvt.d.s[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+42058553[ 	]+fcvt.d.s[ 	]+a0,a1

gas/testsuite/gas/riscv/zdinx-32-regpair.s

@@ -0,0 +1,62 @@
+target:
+	fadd.d	a0, a2, a4
+	fadd.d	a0, a2, a4, rne
+	fsub.d	a0, a2, a4
+	fsub.d	a0, a2, a4, rne
+	fmul.d	a0, a2, a4
+	fmul.d	a0, a2, a4, rne
+	fdiv.d	a0, a2, a4
+	fdiv.d	a0, a2, a4, rne
+	fsqrt.d	a0, a2
+	fsqrt.d	a0, a2, rne
+	fmin.d	a0, a2, a4
+	fmax.d	a0, a2, a4
+	fmadd.d	a0, a2, a4, a6
+	fmadd.d	a0, a2, a4, a6, rne
+	fnmadd.d	a0, a2, a4, a6
+	fnmadd.d	a0, a2, a4, a6, rne
+	fmsub.d	a0, a2, a4, a6
+	fmsub.d	a0, a2, a4, a6, rne
+	fnmsub.d	a0, a2, a4, a6
+	fnmsub.d	a0, a2, a4, a6, rne
+	fsgnj.d	a0, a2, a4
+	fsgnjn.d	a0, a2, a4
+	fsgnjx.d	a0, a2, a4
+	fmv.d	a0, a2
+	fneg.d	a0, a2
+	fabs.d	a0, a2
+	# Compare instructions: destination is a GPR
+	feq.d	a0, a2, a4
+	feq.d	a1, a2, a4
+	flt.d	a0, a2, a4
+	flt.d	a1, a2, a4
+	fle.d	a0, a2, a4
+	fle.d	a1, a2, a4
+	fgt.d	a0, a2, a4
+	fgt.d	a1, a2, a4
+	fge.d	a0, a2, a4
+	fge.d	a1, a2, a4
+	# fclass instruction: destination is a GPR
+	fclass.d	a0, a2
+	fclass.d	a1, a2
+	# fcvt instructions (float-int or int-float;
+	#                    integer operand register can be odd)
+	fcvt.w.d	a0, a2
+	fcvt.w.d	a0, a2, rne
+	fcvt.w.d	a1, a2
+	fcvt.w.d	a1, a2, rne
+	fcvt.wu.d	a0, a2
+	fcvt.wu.d	a0, a2, rne
+	fcvt.wu.d	a1, a2
+	fcvt.wu.d	a1, a2, rne
+	fcvt.d.w	a0, a2
+	fcvt.d.w	a0, a1
+	fcvt.d.wu	a0, a2
+	fcvt.d.wu	a0, a1
+	# fcvt instructions (float-float; FP32 operand can be odd)
+	fcvt.s.d	a0, a2
+	fcvt.s.d	a0, a2, rne
+	fcvt.s.d	a1, a2
+	fcvt.s.d	a1, a2, rne
+	fcvt.d.s	a0, a2
+	fcvt.d.s	a0, a1

gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d

@@ -0,0 +1,12 @@
+#as: -march=rv32ima_zqinx
+#source: zqinx-32-regpair-dis.s
+#objdump: -dr -Mnumeric
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+06c47253[ 	]+fadd.q[ 	]+x4,x8,x12
+[ 	]+[0-9a-f]+:[ 	]+06d4f2d3[ 	]+\.4byte[ 	]+0x6d4f2d3
+[ 	]+[0-9a-f]+:[ 	]+06e57353[ 	]+\.4byte[ 	]+0x6e57353