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cleanup and constids
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@mmicko
mmicko committed Nov 27, 2024
1 parent 77a97f9 commit f62c33f
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Showing 6 changed files with 233 additions and 232 deletions.
250 changes: 125 additions & 125 deletions himbaechel/uarch/ng-ultra/bitstream.cc
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13 changes: 13 additions & 0 deletions himbaechel/uarch/ng-ultra/constids.inc
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Original file line number Diff line number Diff line change
Expand Up @@ -909,6 +909,8 @@ X(WEQ)
X(WRSTI1)
X(WRSTI2)
X(WRSTO)
X(WRSTI)
X(RRSTI)

// GBC
X(GBC)
Expand Down Expand Up @@ -4525,6 +4527,7 @@ X(NX_CTX_U)
// NX_CY
X(NX_CY)
X(add_carry)
X(shifter)

// NX_DES
X(NX_DES)
Expand Down Expand Up @@ -4565,6 +4568,9 @@ X(NX_DFR)
//X(path)
//X(ring)

// NX_DDFR_U
X(NX_DDFR_U)

// NX_DSP
X(NX_DSP)
X(raw_config0)
Expand Down Expand Up @@ -6011,3 +6017,10 @@ X(LOC)
X(lut_used)
X(dff_used)

X(type)

// Timing
X(BEYOND_FE_LUT)

// csv
X(registered)
34 changes: 17 additions & 17 deletions himbaechel/uarch/ng-ultra/csv.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -209,25 +209,25 @@ void NgUltraImpl::parse_csv(const std::string &filename)
}
std::vector<CellInfo *> dest = get_cells(arg_iobname);
for (auto c : dest) {
c->params[ctx->id("iobname")] = arg_iobname;
c->params[ctx->id("location")] = arg_location;
c->params[ctx->id("standard")] = arg_standard;
c->params[ctx->id("drive")] = arg_drive;
c->params[ctx->id("slewRate")] = arg_slewRate;
c->params[ctx->id("inputDelayLine")] = arg_inputDelayLine;
c->params[ctx->id("outputDelayLine")] = arg_outputDelayLine;
c->params[ctx->id("inputDelayOn")] = std::string((std::stoi(arg_inputDelayLine)!=0) ? "True" : "False");
c->params[ctx->id("outputDelayOn")] = std::string((std::stoi(arg_outputDelayLine)!=0) ? "True" : "False");
c->params[ctx->id("differential")] = arg_differential;
c->params[ctx->id("weakTermination")] = arg_weakTermination;
c->params[id_iobname] = arg_iobname;
c->params[id_location] = arg_location;
c->params[id_standard] = arg_standard;
c->params[id_drive] = arg_drive;
c->params[id_slewRate] = arg_slewRate;
c->params[id_inputDelayLine] = arg_inputDelayLine;
c->params[id_outputDelayLine] = arg_outputDelayLine;
c->params[id_inputDelayOn] = std::string((std::stoi(arg_inputDelayLine)!=0) ? "True" : "False");
c->params[id_outputDelayOn] = std::string((std::stoi(arg_outputDelayLine)!=0) ? "True" : "False");
c->params[id_differential] = arg_differential;
c->params[id_weakTermination] = arg_weakTermination;
if (!arg_termination.empty()) {
c->params[ctx->id("termination")] = arg_termination;
c->params[ctx->id("terminationReference")] = arg_terminationReference;
c->params[id_termination] = arg_termination;
c->params[id_terminationReference] = arg_terminationReference;
}
c->params[ctx->id("turbo")] = arg_turbo;
c->params[ctx->id("inputSignalSlope")] = arg_inputSignalSlope;
c->params[ctx->id("outputCapacity")] = arg_outputCapacity;
c->params[ctx->id("registered")] = arg_registered;
c->params[id_turbo] = arg_turbo;
c->params[id_inputSignalSlope] = arg_inputSignalSlope;
c->params[id_outputCapacity] = arg_outputCapacity;
c->params[id_registered] = arg_registered;
}
if (dest.size()==0)
log_warning("Pad with name '%s' not found in netlist.\n", arg_iobname.c_str());
Expand Down
2 changes: 1 addition & 1 deletion himbaechel/uarch/ng-ultra/gen/arch_gen.py
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Original file line number Diff line number Diff line change
Expand Up @@ -348,7 +348,7 @@ def create_tile_types(ch: Chip, bels, bel_pins, crossbars, interconnects, muxes,
if len(items)==1:
sub_type = tile_type
else:
sub_type = tile_type + "_"+str(num)
sub_type = f"{tile_type}_{num}"
tt = ch.create_tile_type(sub_type)

def lookup_site_wire(canon_name):
Expand Down
10 changes: 5 additions & 5 deletions himbaechel/uarch/ng-ultra/ng_ultra.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -279,7 +279,7 @@ bool NgUltraImpl::update_bff_to_csc(CellInfo *cell, BelId bel, PipId dst_pip)
continue;
IdString dst = ctx->getWireName(ctx->getPipDstWire(pip2))[1];
if (boost::ends_with(dst.c_str(ctx),".DS")) {
cell->setParam(ctx->id("type"), Property("CSC"));
cell->setParam(id_type, Property("CSC"));
return true;
}
}
Expand All @@ -303,7 +303,7 @@ bool NgUltraImpl::update_bff_to_scc(CellInfo *cell, BelId bel, PipId dst_pip)
continue;
IdString dst = ctx->getWireName(ctx->getPipSrcWire(pip2))[1];
if (boost::starts_with(dst.c_str(ctx),"SYSTEM.ST1")) {
cell->setParam(ctx->id("type"), Property("SCC"));
cell->setParam(id_type, Property("SCC"));
return true;
}
}
Expand Down Expand Up @@ -339,7 +339,7 @@ void NgUltraImpl::postRoute()
case id_BEYOND_FE.index :
if (extra_data.input==0) {
// set bypass mode for DFF
cell->setParam(ctx->id("type"), Property("BFF"));
cell->setParam(id_type, Property("BFF"));
cell->params[id_dff_used] = Property(1,1);
// Note: no conflict, CSC and SCC modes are never available on same position
if (update_bff_to_csc(cell, bel, w.second.pip))
Expand All @@ -358,7 +358,7 @@ void NgUltraImpl::postRoute()
cell->type = id_WFB;
break;
case id_GCK.index : gck_bypass++;
cell->setParam(ctx->id("std_mode"), extra_data.input == 0 ? Property("BYPASS") : Property("CSC"));
cell->setParam(id_std_mode, extra_data.input == 0 ? Property("BYPASS") : Property("CSC"));
break;
default:
log_error("Unmaped bel type '%s' for routing\n",type.c_str(ctx));
Expand Down Expand Up @@ -479,7 +479,7 @@ struct SectionFEWorker
}
const auto &bel_data = chip_bel_info(ctx->chip_info, bel);
const auto &extra_data = *reinterpret_cast<const NGUltraBelExtraDataPOD *>(bel_data.extra_data.get());
std::string type = str_or_default(cell->params, ctx->id("type"), "");
std::string type = str_or_default(cell->params, id_type, "");
if (type=="CSC" && (extra_data.flags & BEL_EXTRA_FE_CSC) == 0) return false; // No CSC capability on FE
if (type=="SCC" && (extra_data.flags & BEL_EXTRA_FE_SCC) == 0) return false; // No SCC capability on FE
if (extra_data.flags & BEL_EXTRA_FE_CSC)
Expand Down
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