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Example HDL: AXI DDS Compiler, Simulink period set to 1 despite frequency is 1Mhz #36

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mohammadsdtmnd opened this issue Mar 22, 2024 · 0 comments

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@mohammadsdtmnd
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mohammadsdtmnd commented Mar 22, 2024

Hello, I want to check the output frequency of DDS with spectrum analyzer. But the example told to set Simulink period in Vitis hub settings to 1. This causes spectrum analyzer to show signal frequency incorrectly.
I really can't understand why this tutorial creator set the Simulink period to 1 instead of 1/100e6 to help fully see output frequency. Setting that to 1 only creates ambiguity, doesn't it?
Though I've set Simulink period to 1/100e6 and the output of DDS became 0.
Any help will be appreciated.

@mohammadsdtmnd mohammadsdtmnd changed the title Example HDL: AXI DDS Compiler, simulink period problem Example HDL: AXI DDS Compiler, Simulink period set to 1 despite frequency is 1Mhz Mar 22, 2024
robgraessle added a commit that referenced this issue Nov 19, 2024
Add Export to Vitis tutorial
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