Move output variables to init

WISDEM · Sep 25, 2020 · 30c5d3c · 30c5d3c
1 parent f53685e
commit 30c5d3c
Showing 1 changed file with 19 additions and 22 deletions.
diff --git a/ROSCO_testing/ROSCO_testing.py b/ROSCO_testing/ROSCO_testing.py
@@ -57,6 +57,23 @@ def __init__(self, **kwargs):
         self.FAST_directory = os.path.join(os.getcwd(), '../Test_Cases/NREL-5MW')
         self.FAST_InputFile = 'NREL-5MW.fst'
 
+        # Desired output channesl
+        self.var_out = [
+                        'BldPitch1', 'BldPitch2', 'BldPitch3', 'GenTq', 'GenPwr', 'RotSpeed',
+                        'TipDxc1', 'TipDyc1', 'TipDzc1', 'TipDxc2',
+                        'TipDyc2', 'TipDzc2', 'TipDxc3', 'TipDyc3', 'TipDzc3',
+                        'RootMxc1', 'RootMyc1', 'RootMzc1',
+                        'RootMxc2', 'RootMyc2', 'RootMzc2',
+                        'RootMxc3', 'RootMyc3', 'RootMzc3',
+                        'RootMxb1', 'RootMyb1', 'RootMzb1',
+                        'RootMxb2', 'RootMyb2', 'RootMzb2',
+                        'RootMxb3', 'RootMyb3', 'RootMzb3',
+                        'TwrBsMxt', 'TwrBsMyt', 'TwrBsMzt',
+                        'TwrBsFxt', 'TwrBsFyt', 'TwrBsFzt',
+                        'Wind1VelX', 'Wind1VelY', 'Wind1VelZ',
+                        'RtVAvgxh', 'RtVAvgyh', 'RtVAvgzh'
+                        ]
+
         if self.cores > mp.cpu_count():
             self.parallel_cores = mp.cpu_count()
 
@@ -165,17 +182,7 @@ def ROSCO_Test_lite(self, more_case_inputs=None):
         case_list, case_name_list = iec.execute(case_inputs=case_inputs)
 
         # Ensure proper output channels
-        var_out =  ['BldPitch1', 'BldPitch2', 'BldPitch3', 'GenTq', 'GenPwr', 'RotSpeed']
-        var_out += ["TipDxc1", "TipDyc1", "TipDzc1", "TipDxc2",
-                    "TipDyc2", "TipDzc2", "TipDxc3", "TipDyc3", "TipDzc3"]
-        var_out += ["RootMxc1", "RootMyc1", "RootMzc1",
-                     "RootMxc2", "RootMyc2", "RootMzc2",
-                     "RootMxc3", "RootMyc3", "RootMzc3",
-                     "RootMxb1", "RootMyb1", "RootMzb1",
-                     "RootMxb2", "RootMyb2", "RootMzb2",
-                     "RootMxb3", "RootMyb3", "RootMzb3"]  
-        var_out += ["TwrBsMxt", "TwrBsMyt", "TwrBsMzt",
-                     "TwrBsFxt", "TwrBsFyt", "TwrBsFzt"]
+        var_out = self.var_out
 
         channels = {}
         for var in var_out:
@@ -312,17 +319,7 @@ def ROSCO_Test_heavy(self, more_case_inputs=None):
         case_list, case_name_list = iec.execute(case_inputs=case_inputs)
 
         # Ensure proper output channels
-        var_out = ['BldPitch1', 'BldPitch2', 'BldPitch3', 'GenTq', 'GenPwr', 'RotSpeed']
-        var_out += ["TipDxc1", "TipDyc1", "TipDzc1", "TipDxc2",
-                     "TipDyc2", "TipDzc2", "TipDxc3", "TipDyc3", "TipDzc3"]
-        var_out += ["RootMxc1", "RootMyc1", "RootMzc1", 
-                     "RootMxc2", "RootMyc2", "RootMzc2", 
-                     "RootMxc3", "RootMyc3", "RootMzc3",
-                     "RootMxb1", "RootMyb1", "RootMzb1",
-                     "RootMxb2", "RootMyb2", "RootMzb2",
-                     "RootMxb3", "RootMyb3", "RootMzb3"]
-        var_out += ["TwrBsMxt", "TwrBsMyt", "TwrBsMzt",
-                     "TwrBsFxt", "TwrBsFyt", "TwrBsFzt"]
+        var_out = self.var_out
 
         channels = {}
         for var in var_out: