use pathlib instead of join, dirname, etc.

docs/conf.py

@@ -2,7 +2,7 @@
 
 import os
 import sys
-from os.path import join
+from pathlib import Path
 
 # blog_title = u"VUnit Blog"
 # blog_baseurl = "http://vunit.github.io"
@@ -70,9 +70,9 @@
 
 html_static_path = ["_static"]
 
-html_logo = join(html_static_path[0], "VUnit_logo_420x420.png")
+html_logo = str(Path(html_static_path[0]) / "VUnit_logo_420x420.png")
 
-html_favicon = join(html_static_path[0], "vunit.ico")
+html_favicon = str(Path(html_static_path[0]) / "vunit.ico")
 
 # Output file base name for HTML help builder.
 htmlhelp_basename = "vunitdoc"

examples/vhdl/vivado/vivado_util.py

@@ -5,7 +5,7 @@
 # Copyright (c) 2014-2020, Lars Asplund [email protected]
 
 import sys
-from os.path import join, exists, abspath, dirname
+from pathlib import Path
 from vunit.sim_if.factory import SIMULATOR_FACTORY
 from vunit.vivado import (
     run_vivado,
@@ -19,35 +19,40 @@ def add_vivado_ip(vunit_obj, output_path, project_file):
     Add vivado (and compile if necessary) vivado ip to vunit project.
     """
 
-    if not exists(project_file):
+    if not Path(project_file).exists():
         print("Could not find vivado project %s" % project_file)
         sys.exit(1)
 
-    standard_library_path = join(output_path, "standard")
+    opath = Path(output_path)
+
+    standard_library_path = str(opath / "standard")
     compile_standard_libraries(vunit_obj, standard_library_path)
 
-    project_ip_path = join(output_path, "project_ip")
+    project_ip_path = str(opath / "project_ip")
     add_project_ip(vunit_obj, project_file, project_ip_path)
 
 
 def compile_standard_libraries(vunit_obj, output_path):
     """
     Compile Xilinx standard libraries using Vivado TCL command
     """
-    done_token = join(output_path, "all_done.txt")
+    done_token = str(Path(output_path) / "all_done.txt")
 
     simulator_class = SIMULATOR_FACTORY.select_simulator()
 
-    if not exists(done_token):
-        print("Compiling standard libraries into %s ..." % abspath(output_path))
+    if not Path(done_token).exists():
+        print(
+            "Compiling standard libraries into %s ..."
+            % str(Path(output_path).resolve())
+        )
         simname = simulator_class.name
 
         # Vivado calls rivierapro for riviera
         if simname == "rivierapro":
             simname = "riviera"
 
         run_vivado(
-            join(dirname(__file__), "tcl", "compile_standard_libs.tcl"),
+            str(Path(__file__).parent / "tcl" / "compile_standard_libs.tcl"),
             tcl_args=[
                 simname,
                 simulator_class.find_prefix().replace("\\", "/"),
@@ -57,12 +62,13 @@ def compile_standard_libraries(vunit_obj, output_path):
 
     else:
         print(
-            "Standard libraries already exists in %s, skipping" % abspath(output_path)
+            "Standard libraries already exists in %s, skipping"
+            % str(Path(output_path).resolve())
         )
 
     for library_name in ["unisim", "unimacro", "unifast", "secureip", "xpm"]:
-        path = join(output_path, library_name)
-        if exists(path):
+        path = str(Path(output_path) / library_name)
+        if Path(path).exists():
             vunit_obj.add_external_library(library_name, path)
 
     with open(done_token, "w") as fptr:
@@ -79,16 +85,16 @@ def add_project_ip(vunit_obj, project_file, output_path, vivado_path=None, clean
     returns the list of SourceFile objects added
     """
 
-    compile_order_file = join(output_path, "compile_order.txt")
+    compile_order_file = str(Path(output_path) / "compile_order.txt")
 
-    if clean or not exists(compile_order_file):
+    if clean or not Path(compile_order_file).exists():
         create_compile_order_file(
             project_file, compile_order_file, vivado_path=vivado_path
         )
     else:
         print(
             "Vivado project Compile order already exists, re-using: %s"
-            % abspath(compile_order_file)
+            % str(Path(compile_order_file).resolve())
         )
 
     return add_from_compile_order_file(vunit_obj, compile_order_file)

tests/acceptance/artificial/verilog/run.py

@@ -4,14 +4,14 @@
 #
 # Copyright (c) 2014-2020, Lars Asplund [email protected]
 
-from os.path import join, dirname
+from pathlib import Path
 from vunit.verilog import VUnit
 
-root = dirname(__file__)
+ROOT = Path(__file__).parent
 
 VU = VUnit.from_argv()
 LIB = VU.add_library("lib")
-LIB.add_source_files(join(root, "*.sv"), defines={"DEFINE_FROM_RUN_PY": ""})
+LIB.add_source_files(ROOT / "*.sv", defines={"DEFINE_FROM_RUN_PY": ""})
 
 
 def configure_tb_with_parameter_config():
@@ -35,7 +35,7 @@ def configure_tb_with_parameter_config():
     )
 
     def post_check(output_path):
-        with open(join(output_path, "post_check.txt"), "r") as fptr:
+        with (Path(output_path) / "post_check.txt").open("r") as fptr:
             return fptr.read() == "Test 4 was here"
 
     tests[4].add_config(
@@ -49,7 +49,7 @@ def post_check(output_path):
 
 def configure_tb_same_sim_all_pass(ui):
     def post_check(output_path):
-        with open(join(output_path, "post_check.txt"), "r") as fptr:
+        with (Path(output_path) / "post_check.txt").open("r") as fptr:
             return fptr.read() == "Test 3 was here"
 
     module = ui.library("lib").module("tb_same_sim_all_pass")
@@ -59,6 +59,6 @@ def post_check(output_path):
 configure_tb_with_parameter_config()
 configure_tb_same_sim_all_pass(VU)
 LIB.module("tb_other_file_tests").scan_tests_from_file(
-    join(root, "other_file_tests.sv")
+    str(ROOT / "other_file_tests.sv")
 )
 VU.main()

tests/acceptance/artificial/vhdl/run.py

@@ -4,14 +4,14 @@
 #
 # Copyright (c) 2014-2020, Lars Asplund [email protected]
 
-from os.path import join, dirname
+from pathlib import Path
 from vunit import VUnit
 
-root = dirname(__file__)
+ROOT = Path(__file__).parent
 
 VU = VUnit.from_argv()
 LIB = VU.add_library("lib")
-LIB.add_source_files(join(root, "*.vhd"))
+LIB.add_source_files(ROOT / "*.vhd")
 
 
 def configure_tb_with_generic_config():
@@ -33,7 +33,7 @@ def configure_tb_with_generic_config():
     )
 
     def post_check(output_path):
-        with open(join(output_path, "post_check.txt"), "r") as fptr:
+        with (Path(output_path) / "post_check.txt").open("r") as fptr:
             return "Test 4 was here" in fptr.read()
 
     tests[4].add_config(
@@ -45,7 +45,7 @@ def post_check(output_path):
 
 def configure_tb_same_sim_all_pass(ui):
     def post_check(output_path):
-        with open(join(output_path, "post_check.txt"), "r") as fptr:
+        with (Path(output_path) / "post_check.txt").open("r") as fptr:
             return "Test 3 was here" in fptr.read()
 
     ent = ui.library("lib").entity("tb_same_sim_all_pass")
@@ -93,6 +93,6 @@ def configure_tb_assert_stop_level(ui):
 LIB.entity("tb_no_generic_override").set_generic("g_val", False)
 LIB.entity("tb_ieee_warning").test("pass").set_sim_option("disable_ieee_warnings", True)
 LIB.entity("tb_other_file_tests").scan_tests_from_file(
-    join(root, "other_file_tests.vhd")
+    str(ROOT / "other_file_tests.vhd")
 )
 VU.main()

tests/acceptance/test_artificial.py

@@ -9,13 +9,15 @@
 """
 
 import unittest
-from os.path import join, dirname
+from pathlib import Path
 from os import environ
 from subprocess import call
 import sys
 from tests.common import check_report
 from vunit.sim_if.common import has_simulator, simulator_is
 
+ROOT = Path(__file__).parent
+
 
 @unittest.skipUnless(has_simulator(), "Requires simulator")
 class TestVunitArtificial(unittest.TestCase):
@@ -26,18 +28,14 @@ class TestVunitArtificial(unittest.TestCase):
 
     def setUp(self):
         if simulator_is("activehdl"):
-            self.output_path = join(dirname(__file__), "artificial_out")
+            self.output_path = str(ROOT / "artificial_out")
         else:
             # Spaces in path intentional to verify that it is supported
-            self.output_path = join(dirname(__file__), "artificial _out")
+            self.output_path = str(ROOT / "artificial _out")
 
-        self.report_file = join(self.output_path, "xunit.xml")
-        self.artificial_run_vhdl = join(
-            dirname(__file__), "artificial", "vhdl", "run.py"
-        )
-        self.artificial_run_verilog = join(
-            dirname(__file__), "artificial", "verilog", "run.py"
-        )
+        self.report_file = str(Path(self.output_path) / "xunit.xml")
+        self.artificial_run_vhdl = str(ROOT / "artificial" / "vhdl" / "run.py")
+        self.artificial_run_verilog = str(ROOT / "artificial" / "verilog" / "run.py")
 
     @unittest.skipUnless(
         simulator_is("modelsim", "rivierapro"),

tests/acceptance/test_dependencies.py

@@ -11,18 +11,20 @@
 
 
 import unittest
-from os.path import join, dirname
+from pathlib import Path
 from vunit import VUnit
 
+ROOT = Path(__file__).parent
+
 
 class TestDependencies(unittest.TestCase):
     """
     Test to expose simulator dependency requirements
     """
 
     def setUp(self):
-        self.data_path = join(dirname(__file__), "dependencies")
-        self.output_path = join(dirname(__file__), "dependencies_vunit_out")
+        self.data_path = str(ROOT / "dependencies")
+        self.output_path = str(ROOT / "dependencies_vunit_out")
 
     def test_package_body_dependencies(self):
         """
@@ -36,9 +38,11 @@ def run(value):
             Utility function to first run with pkg_body1 then pkg_body2
             """
 
-            tb_pkg_file_name = join(self.data_path, "tb_pkg.vhd")
-            pkg_file_name = join(self.data_path, "pkg.vhd")
-            pkg_body_file_name = join(self.data_path, "pkg_body%i.vhd" % value)
+            dpath = Path(self.data_path)
+
+            tb_pkg_file_name = str(dpath / "tb_pkg.vhd")
+            pkg_file_name = str(dpath / "pkg.vhd")
+            pkg_body_file_name = str(dpath / ("pkg_body%i.vhd" % value))
 
             argv = ["--output-path=%s" % self.output_path, "-v"]
             if value == 1: