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JSON --> RDL conversion and regfile registers overlapping after elaboration
#225
opened Oct 24, 2024 by
anjpar
[BUG] Verilog preprocessor,
ifdef around
include statement
#223
opened Oct 15, 2024 by
Risto97
1 task done
Compatibility between UDP Something isn't working
default
property and UDPDefinition.default_assignment
bug
#213
opened May 8, 2024 by
maltaisn
[FEATURE] property_src_ref needed for UserEnum and UserEnumMember
feature
New feature or request
#200
opened Jan 26, 2024 by
kjeldbeg
Set abbreviated Node.type_name for long parameterized types
feature
New feature or request
#198
opened Jan 7, 2024 by
erang20
Add support for assigning references in importer API
feature
New feature or request
#183
opened Jul 19, 2023 by
amykyta3
Software-writable field spanning multiple words should cause error message (accesswidth/regwidth problem)
#178
opened Jun 13, 2023 by
kjeldbeg
ProTip!
Exclude everything labeled
bug
with -label:bug.