Fix I/O placement for sparse apps

StanfordAHA · Nov 5, 2024 · 63cd00b · 63cd00b
1 parent 1502201
commit 63cd00b
Showing 1 changed file with 8 additions and 3 deletions.
diff --git a/tests/test_memory_core/build_tb.py b/tests/test_memory_core/build_tb.py
@@ -131,8 +131,12 @@ def __init__(self, nlb: NetlistBuilder = None, graph: Graph = None, bespoke=Fals
 
         self.height = height
         self.width = width
-        self.input_ctr = 0
-        self.output_ctr = 1
+
+        # Matrix unit hack 
+        #self.input_ctr = 0
+        self.input_ctr = 1
+        #self.output_ctr = 1
+        self.output_ctr = 2
 
         self.glb_to_io_mapping = {}
         self.glb_cores = {}
@@ -156,7 +160,7 @@ def __init__(self, nlb: NetlistBuilder = None, graph: Graph = None, bespoke=Fals
             # CGRA Path
             self.register_cores()
             self.connect_cores()
-
+        
             print("Balancing SAM Graph with FIFOs")
             # ### Balance SAM graph with interconnect FIFOs #####
             new_netlist = copy.deepcopy(self.nlb._netlist)
@@ -174,6 +178,7 @@ def __init__(self, nlb: NetlistBuilder = None, graph: Graph = None, bespoke=Fals
                     G.add_edge(src, dest, name=edge)
                 if "buffer_passthrough" in src_name or "buffer_passthrough" in dest_name:
                     G.add_edge(src, dest, name=edge)
+
 
             # break cycles
             cycles = list(nx.simple_cycles(G))