RELEASE NOTES FOR NICTA MODIFIED VERSION 4.2
========================================
This version of Chronos has been modified by NICTA (now Data61) to support the
ARM architecture, and the iMX.31 processor in particular based on SimpleScalar/ARM. Please refer to the
documentation of our WCET tools for how to use Chronos as part of that
toolchain.

RELEASE NOTES FOR PROTOTYPE VERSION 4.1
=========================================
This is a prototype release of Chronos with scope-aware data cache analysis.

Currently, it only supports scope-aware analysis of L1 data cache. Some 
features (e.g. infeasible path detection, branch prediction, out-of-order 
pipeline analysis) are disabled (check the sample processor.opt file 
included in the package).

This prototype requires manually inline all procedures for successful 
data address analysis (see adpcm benchmark included). For triangular loop, 
you need to create file <binary file name>.econ and set extra loop conditions 
to help Chronos recognize them:
Contrainst format: <type> L1_id L2_id k
type = "eql" : L1's loop bound <= L2's iteration + k 
(check the bsort100 benchmark included in the package)

We look forward to your suggestions. Feel free to contact us at
([email protected] or [email protected]) to give 
your valuable comments.

RELEASE NOTES FOR VERSION 4.0
==============================
Chronos has been extended with a level 2 unified cache modeling. Additionally 
chronos can also support a level 2 instruction cache and/or a level 1 data 
cache. Two sample processor configuration files are included in the package 
which are not analyzable previously by Chronos:

--- processor.opt (with a level 2 instruction cache and a level 1 data cache)
--- processor1.opt (with a level 2 unified cache)

Currently, these extensions are supported only through the command line. 

==> A note about the memory manager

Level 2 unified cache analysis reqquires many cache analysis and therefore 
also consumes a significant amount of memory. The current memory manager 
is implemented under a flag "MEM_FREE" which is enabled in the Makefile. 
Enabling this flag mostly free up all memories not used any more (garbage).
For a faster analysis but with more memory consumptions, users may consider 
removing this flag from the "Makefile".

We look forward for your suggestions. Feel free to contact us 
([email protected]) to give your valuable comments.

QUICK START
===========
1. to formulate an ILP problem:
   - command:
     $ est <benchmark>
   - example:
     $ est ../benchmarks/matsum/matsum
   - input files:
     * <benchmark>
     * <benchmark>.cons
   - output files:
     * <benchmark>.lp

2. to generate CFG file:
   - command:
     $ est -run CFG <benchmark>
   - example:
     $ est -run CFG ../benchmarks/matsum/matsum
   - input files:
     * <benchmark>
   - output files:
     * <benchmark>.cfg

3. to dump processor configurations (pipeline, branch prediction, cache)
   - command:
     $ est -run OPT <output_file>
   - example:
     $ est -run OPT processor.opt
   - input files: NONE
   - output files:
     * <output_file>

4. to invoke the ILP solver
   - command:
     $ solve <benchmark>.lp
   - example:
     $ solve ../benchmarks/matsum/matsum.lp
   - input files:
     * <benchmark>.ilp
   - output files:
     * wcet_result


ESTIMTATE WITH NON-DEFAULT PROCESSOR OPTIONS
============================================
1. with a configuration file:
   - command:
     $ est -config <opt_file> <benchmark>
   - example: 
     $ est -config processor.opt ../benchmarks/matsum/matsum

2. with commond-line options: consistent with SimpleScalar sim-outorder options
   - example:
   $ est -bpred perfect -cache:il1 none  ../benchmarks/matsum/matsum
   (estimate assuming perfect branch prediction and no instruction cache)


processor options file example (the content in processor.opt)
==============================================================

# instruction fetch queue size (in insts)
-fetch:ifqsize      4 

# branch predictor type {nottaken|taken|perfect|bimod|2lev|comb}
#-bpred             perfect
-bpred              2lev

# bimodal predictor config (<table size>)
-bpred:bimod        4 

# 2-level predictor config (<l1size> <l2size> <hist_size> <xor>)
-bpred:2lev         1 4 2 0 

# combining predictor config (<meta_table_size>)
-bpred:comb         4 

# register update unit (RUU) size
-ruu:size           8 

# l1 inst cache config, i.e., {<config>|dl1|dl2|none}
-cache:il1          il1:16:64:1:l 

# memory access latency (<first_chunk> <inter_chunk>)
-mem:lat            10 2