Update jit_compiler_a64_static.S

src/jit_compiler_a64_static.S

@@ -62,6 +62,9 @@ DECL(randomx_clear_cache):
 	cmp	x0, x1
 	bhs	randomx_clear_cache_exit
 
+	# test
+	ret
+
 	# Read "Cache Type Register, EL0"
 	# https://developer.arm.com/documentation/ddi0488/h/system-control/aarch64-register-descriptions/cache-type-register--el0
 	mrs	x4, ctr_el0
@@ -76,13 +79,13 @@ DECL(randomx_clear_cache):
 	# Invalidate all data cache lines between x0 and x1
 	mov	x2, x0
 randomx_dcache_invalidate_loop:
-	#dc	cvau, x2
+	dc	cvau, x2
 	add	x2, x2, x3
 	cmp	x2, x1
 	blo	randomx_clear_cache_loop
 
 	# Data Synchronization Barrier
-	#dsb	ish
+	dsb	ish
 
 	# [3:0] IminLine
 	# Log2 of the number of words in the smallest cache line of all the Instruction Caches that the processor controls
@@ -93,13 +96,13 @@ randomx_dcache_invalidate_loop:
 	# Invalidate all instruction cache lines between x0 and x1
 	mov	x2, x0
 randomx_clear_cache_loop:
-	#ic	ivau, x2
+	ic	ivau, x2
 	add	x2, x2, x3
 	cmp	x2, x1
 	blo	randomx_clear_cache_loop
 
 	# Instruction Synchronization Barrier
-	#isb	sy
+	isb	sy
 
 randomx_clear_cache_exit:
 	ret