Update jit_compiler_a64_static.S

src/jit_compiler_a64_static.S

@@ -58,21 +58,44 @@ DECL(randomx_icache_invalidate):
 	# x0 = begin
 	# x1 = end
 
-	# range check
+	# Range check
 	cmp	x0, x1
 	bhs	randomx_icache_invalidate_exit
 
-	# get icache line size
-	mrs	x2, ctr_el0
+	# Read "Cache Type Register, EL0"
+	# https://developer.arm.com/documentation/ddi0488/h/system-control/aarch64-register-descriptions/cache-type-register--el0
+	mrs	x4, ctr_el0
+
+	# [19:16] DminLine
+	# Log2 of the number of words in the smallest cache line of all the data and unified caches that the processor controls
+	lsr	x2, x4, 16
 	and	x2, x2, 15
 	mov	x3, 4
 	lsl	x3, x3, x2
 
-	# invalidate all cache lines between x0 and x1
+	# Invalidate all data cache lines between x0 and x1
+	mov	x2, x0
+randomx_dcache_invalidate_loop:
+	dc	cvau, x2
+	add	x2, x2, x3
+	cmp	x2, x1
+	blo	randomx_icache_invalidate_loop
+
+	# Data Synchronization Barrier
+	dsb	ish
+
+	# [3:0] IminLine
+	# Log2 of the number of words in the smallest cache line of all the Instruction Caches that the processor controls
+	and	x2, x4, 15
+	mov	x3, 4
+	lsl	x3, x3, x2
+
+	# Invalidate all instruction cache lines between x0 and x1
+	mov	x2, x0
 randomx_icache_invalidate_loop:
-	ic	ivau, [x0]
-	add	x0, x0, x3
-	cmp	x0, x1
+	ic	ivau, x2
+	add	x2, x2, x3
+	cmp	x2, x1
 	blo	randomx_icache_invalidate_loop
 
 	# Instruction Synchronization Barrier