Updated progress

README.md

@@ -14,6 +14,26 @@ The goal of this repo is to re-create the schematics and create the HDL files so
 On the way to the FPGA code, there will be testable Logisim Circuits and Logisim code that can be converted and tested in C++ using Verilator.
 
 
+## History
+
+Compressed history of the work progress:
+
+| Date               | Description
+|--------------------|-------------------------------------------------------------------------------------------------------------------------------------
+| 11. March 2023     | Received Design Documentation from Lasse Bockelie
+| 21. August 2023    | Logisim Drawings completed for DGA and DELILAH/CGA
+| 03. December 2023  | Using Logisim drawings to start generate Verilog files for DGA and CGA
+| 12. December 2023  | Starting to consolidate all information about PAL chips (PNG for PALASM code, OCR to TXT and write Verilog version of PAL code)
+| 26. December 2023  | Logisim drawings of CPU Board 3202D completed
+| 27. December 2023  | Using Logisim drawings to start generate Verilog files for CPU Board 3202D
+| 11. January 2024   | Most PALASM code has been ported to Verilog
+| January-June 2024  | Adding support chips, refactoring and bugfixing. Adding tests and test results
+| June-November 2024 | No work done
+| 9. November 2024   | Starting up again after a long break. Cleaning up code, refactoring and testing. Connecting everything together.
+| 20. November 2024  | Verilator - Microcode is loaded from ROM to DRAM. MACL microcode starts but fail on STACK operations, and fails on COND operations.
+| 13. December 2024  | Verilator - Microcode MACL starts, CPU test code runs. OPCOM is initialized and communication over UART works.
+
+
 ## Requirements
 
 The minimum requirements to make the CPU work is:

Verilog/readme.md

@@ -14,6 +14,14 @@ Verilator is able to successfully compile and execute microcode load, and contin
 | [PAL](../DesignDocuments/PAL-Code/readme.md)   | No logisim, PALASM source| Verilog compiles - Missing a lot of testcases  | Syntehesis OK, implementation fails   | Hand converted PALASM to Verilog for all PAL's |
 | [Shared](Shared/readme.md)                     |                          | Verilog compiles - Missing a lot of testcases  | Syntehesis OK, implementation fails   | Shared code between the CPU, DGA and 3202D CPU board. Mix of converted logisim and manually created modules |
 
+
+## Run Verilog code using Verilator
+
+There are two folders with test code for verilator
+
+ * sim - contains a simple test of the ND120_TOP module. Saves signal traces to file and is used to verify the Verilog code using GTKWave
+ * runsim - Starts the simulation and runs the microcode load and self-test program. After self test it will enable OPCOM for communication with the CPU.
+
 ## Verilog code status
 
 | Folder           | # of Verilog Files       | Lines of Verilog code  |
@@ -46,6 +54,9 @@ Note: When all modules are merged, number of files and number of lines will be r
 * Clears/Initializes internal registers and sets up UART
 * Runs self-test program for CPU, Test 1-8
 
+* Depending on the input from the PANEL keylock it will either try to automatic load code from storage depending on ALD settings 
+* - or go to OPCOM mode where one can communicate with the CPU via UART
+
 ## Test program verification
 
 ![Screenshot from GTKWave](gtkwave.png)