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[DM/Feature] Basic PCI/PCIe (Peripheral Component Interconnect Express) bus #9014

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merged 2 commits into from
Sep 6, 2024

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GuEe-GUI
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@GuEe-GUI GuEe-GUI commented May 30, 2024

[
PCI/PCIe have better performance and more devices support, such as NVMe, GPU, Powerful NIC (Like RDMA).
PCI/PCIe can access control by IOMMU that the virtualiztion and userspace driver will more safety.
PCI/PCIe device could hot plugging, no design modifications SoC required.
PCI/PCIe on Embedded SoC is popular now.
We make a simple framework to support them.

Feature Lists:

  1. PCI INTx: the INT[A-D] pin IRQ for legacy PCI, work with platform PIC.
  2. MSI/MSI-X: the message write IRQ for PCIe, work with platform's PIC.
  3. PME: we only support the D0, D1, D2, D3HOT, D3COLD init by framework.
  4. Endpoint: a simple EP framework for PCI FPGA or NTB function.
  5. OFW: we only support work on OFW SoC, ACPI support in the future maybe.

Host controller:

  1. Common PCI host controller on ECAM.
  2. Generic PCI host controller on ECAM.

To support this feature, we extended more function:

  1. RT_FIELD_PREP: prepare a bitfield element.
  2. RT_FIELD_GET: extract a bitfield element.
  3. rt_offsetof: member offset of a struct
  4. rt_upper_32_bits: high 32 bits of value.
  5. rt_lower_32_bits: lower 32 bits of value.
  6. rt_upper_16_bits: high 16 bits of value.
  7. rt_lower_16_bits: lower 16 bits of value.
  8. rt_max_t: fix type of max(...).
  9. rt_ilog2: integer logarithm base 2.

]

当前拉取/合并请求的状态 Intent for your PR

必须选择一项 Choose one (Mandatory):

  • 本拉取/合并请求是一个草稿版本 This PR is for a code-review and is intended to get feedback
  • 本拉取/合并请求是一个成熟版本 This PR is mature, and ready to be integrated into the repo

代码质量 Code Quality:

我在这个拉取/合并请求中已经考虑了 As part of this pull request, I've considered the following:

  • 已经仔细查看过代码改动的对比 Already check the difference between PR and old code
  • 代码风格正确,包括缩进空格,命名及其他风格 Style guide is adhered to, including spacing, naming and other styles
  • 没有垃圾代码,代码尽量精简,不包含#if 0代码,不包含已经被注释了的代码 All redundant code is removed and cleaned up
  • 所有变更均有原因及合理的,并且不会影响到其他软件组件代码或BSP All modifications are justified and not affect other components or BSP
  • 对难懂代码均提供对应的注释 I've commented appropriately where code is tricky
  • 代码是高质量的 Code in this PR is of high quality
  • 已经使用formatting 等源码格式化工具确保格式符合RT-Thread代码规范 This PR complies with RT-Thread code specification

@BernardXiong
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RK3568/88的PCIe网卡可以驱动吗?

@GuEe-GUI GuEe-GUI force-pushed the upstream branch 2 times, most recently from 35c2a98 to 631349b Compare June 11, 2024 03:52
@GuEe-GUI GuEe-GUI force-pushed the upstream branch 2 times, most recently from cd89861 to 9d93e59 Compare July 9, 2024 10:31
@GuEe-GUI GuEe-GUI marked this pull request as draft August 1, 2024 08:46
1. RT_FIELD_PREP: prepare a bitfield element.
2. RT_FIELD_GET: extract a bitfield element.
3. rt_offsetof: member offset of a struct
4. rt_upper_32_bits: high 32 bits of value.
5. rt_lower_32_bits: lower 32 bits of value.
6. rt_upper_16_bits: high 16 bits of value.
7. rt_lower_16_bits: lower 16 bits of value.
8. rt_max_t: fix type of max(...).
9. rt_ilog2: integer logarithm base 2.

Signed-off-by: GuEe-GUI <[email protected]>
@GuEe-GUI GuEe-GUI marked this pull request as ready for review August 26, 2024 09:36
@GuEe-GUI GuEe-GUI marked this pull request as draft August 26, 2024 09:36
@GuEe-GUI GuEe-GUI marked this pull request as ready for review August 26, 2024 09:37
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GuEe-GUI commented Aug 27, 2024

RK3568/88的PCIe网卡可以驱动吗?

网卡部分涉及到 PHY 框架改进还没完成,在当前 PCI 框架下,对 ROCK 3A RK3568 上尝试 NVME on PCI + MSI 中断方式驱动可以工作。

…s) bus

PCI/PCIe have better performance and more devices support, such as
NVMe, GPU, Powerful NIC (Like RDMA). PCI/PCIe can access control by
IOMMU that the virtualiztion and userspace driver will more safety.
PCI/PCIe device could hot plugging, no design modifications SoC required,
PCI/PCIe on Embedded SoC is popular now.
We make a simple framework to support them.

Feature Lists:
1.PCI INTx: the INT[A-D] pin IRQ for legacy PCI, work with platform PIC.
2.MSI/MSI-X: the message write IRQ for PCIe, work with platform's PIC.
3.PME: we only support the D0, D1, D2, D3HOT, D3COLD init by framework.
4.Endpoint: a simple EP framework for PCI FPGA or NTB function.
5.OFW: we only support work on OFW SoC, ACPI support in the future maybe.

Host controller:
1. Common PCI host controller on ECAM.
2. Generic PCI host controller on ECAM.

Signed-off-by: GuEe-GUI <[email protected]>
@BernardXiong BernardXiong added +1 Agree +1 wait_+2 wait for "+2" to confirm labels Sep 4, 2024
@mysterywolf mysterywolf merged commit 2168ed8 into RT-Thread:master Sep 6, 2024
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3 participants