[bsp][cvitek] add icache opration

RT-Thread · Dec 2, 2024 · 4b9eb0e · 4b9eb0e
1 parent a181fb4
commit 4b9eb0e
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Showing 3 changed files with 30 additions and 0 deletions.
diff --git a/bsp/cvitek/c906_little/Kconfig b/bsp/cvitek/c906_little/Kconfig
@@ -14,6 +14,7 @@ config BSP_USING_C906_LITTLE
     bool
     select ARCH_RISCV64
     select ARCH_RISCV_FPU_D
+    select RT_USING_CACHE
     select RT_USING_COMPONENTS_INIT
     select RT_USING_USER_MAIN
     default y

diff --git a/bsp/cvitek/c906_little/board/cache.c b/bsp/cvitek/c906_little/board/cache.c
@@ -5,6 +5,7 @@
  *
  * Change Logs:
  * Date           Author       Notes
+ * 2024/11/27     zdtyuiop4444 Add Icache operation
  * 2024/11/26     zdtyuiop4444 The first version
  */
 
@@ -34,3 +35,25 @@ inline void rt_hw_cpu_dcache_ops(int ops, void* addr, int size)
         break;
     }
 }
+
+inline void rt_hw_cpu_icache_enable(void)
+{
+    asm volatile("csrs mhcr, %0;" ::"rI"(0x1));
+}
+
+inline void rt_hw_cpu_icache_disable(void)
+{
+    asm volatile("csrc mhcr, %0;" ::"rI"(0x1));
+}
+
+inline void rt_hw_cpu_icache_ops(int ops, void* addr, int size)
+{
+    switch (ops)
+    {
+    case RT_HW_CACHE_INVALIDATE:
+        CACHE_OP_RANGE(ICACHE_IPA_A0, start, size);
+        break;
+    default:
+        break;
+    }
+}
diff --git a/bsp/cvitek/c906_little/board/cache.h b/bsp/cvitek/c906_little/board/cache.h
@@ -5,6 +5,7 @@
  *
  * Change Logs:
  * Date           Author       Notes
+ * 2024/11/27     zdtyuiop4444 Add Icache operation
  * 2024/11/26     zdtyuiop4444 The first version
  */
 
@@ -29,13 +30,18 @@
  * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
  *   0000001    01011      rs1       000      00000  0001011
  *
+ * icache.ipa rs1 (invalidate)
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ *   0000001    11000      rs1       000      00000  0001011
+ *
  * sync.s
  * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
  *   0000000    11001     00000      000      00000  0001011
  */
 #define DCACHE_IPA_A0 ".long 0x02a5000b"
 #define DCACHE_CPA_A0 ".long 0x0295000b"
 #define DCACHE_CIPA_A0 ".long 0x02b5000b"
+#define ICACHE_IPA_A0 ".long 0x0385000b"
 
 #define SYNC_S ".long 0x0190000b"