cpu/msp430/perriph_usci: fix prescaler values for ACLK #20623
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For super low symbol rates the auxiliary clock (ACLK) is used to conserve power. But with only 32,678 Hz clock just prescaling will result in poor bit timing, hence correct modulation control settings to compensate are needed. Since computing this is too expensive, a look-up table (as switch statement) for the four most common symbol rates was used. The datasheet gave the prescaler values ordered by ascending symbol rate, the switch statement was ordered descending. This changes the order to match the datasheets order and matches the correct prescaler setting to the corresponding symbol rate. Fixes RIOT-OS#20620
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Platform: MSP
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Type: bug
1 task
benpicco
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Apr 26, 2024
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Thx a lot :) |
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Contribution description
For super low symbol rates the auxiliary clock (ACLK) is used to conserve power. But with only 32,678 Hz clock just prescaling will result in poor bit timing, hence correct modulation control settings to compensate are needed. Since computing this is too expensive, a look-up table (as switch statement) for the four most common symbol rates was used.
The datasheet gave the prescaler values ordered by ascending symbol rate, the switch statement was ordered descending. This changes the order to match the datasheets order and matches the correct prescaler setting to the corresponding symbol rate.
Testing procedure
UART on MSP430F2xx is now working for symbol rates of 9600 Bd.
Issues/PRs references
Fixes #20620