cpu/stm32: fix ld script for SRAM4 #19842

gschorcht · 2023-07-22T11:11:34Z

Contribution description

This PR fixes the LD script for STM32.

Since the CCM and SRAM4 length are defined as symbols with perifx _, the LD script didn't use them correctly. Instead of using ccmram_length and sram4_length, _ccmram_length and _sram4_length have to be used. Furthermore, the location counter for the SRAM has to be set to the beginning of SRAM4 to work.

BTW, I don't understand why the ccmram region is defined. There is no section definition that would use it to place code or data with attribute .ccmram.* there.

Without the fix in this PR, defined symbols in tests/sys/malloc for the b-u585i-iot02a board were:

00000000 T _sheap2     <== wrong start position because of wrong location counter
28000000 T _eheap2     <== wrong end position because of `sram4_length` is 0.

Although the tests/sys/malloc crashes for b-u585i-iot02a at the end of the heap (known problem, see here), it uses only the backup RAM before it crashes:

Allocated 512 Bytes at 0x200bf600, total 756072
Allocated 512 Bytes at 0x200bf818, total 756592
Allocated 512 Bytes at 0x200bfa30, total 757112
Allocated 512 Bytes at 0x200bfc48, total 757632
Allocated 512 Bytes at 0x40036408, total 758152
Allocated 512 Bytes at 0x40036610, total 758672
Allocated 512 Bytes at 0x40036818, total 759192

With the fix in this PR, defined symbols in tests/sys/malloc for the b-u585i-iot02a board are:

28000000 T _sheap2     <== correct start position
28004000 T _eheap2     <== correct end position

tests/sys/malloc also crashes for the b-u585i-iot02a at the end of the heap, but it uses also the SRAM4 before it crashes.

Allocated 512 Bytes at 0x200bf600, total 756072
Allocated 512 Bytes at 0x200bf818, total 756592
Allocated 512 Bytes at 0x200bfa30, total 757112
Allocated 512 Bytes at 0x200bfc48, total 757632
Allocated 512 Bytes at 0x40036408, total 758152
Allocated 512 Bytes at 0x40036610, total 758672
Allocated 512 Bytes at 0x40036818, total 759192
Allocated 512 Bytes at 0x28000008, total 759712
Allocated 512 Bytes at 0x28000210, total 760232
Allocated 512 Bytes at 0x28000418, total 760752
...
Allocated 512 Bytes at 0x280038e8, total 774272
Allocated 512 Bytes at 0x28003af0, total 774792
Allocated 512 Bytes at 0x28003cf8, total 775312

Testing procedure

Flash tests/sys/malloc and use MAX_MEM limit to stop malloc before the crash:
```
CFLAGS='-DMAX_MEM=774800 -DCHUNK_SIZE=512 -DDEBUG_ASSERT_VERBOSE' \
BOARD=b-u585i-iot02a make -j8 -C tests/sys/malloc flash
```
Without the PR it crashes at the end of the backup RAM. With the PR it works.

Check _sheap2 and _eheap2 with

nm -s tests/sys/malloc/bin/b-u585i-iot02a/tests_malloc.elf | grep heap2 | sort

Without the PR it will be:

00000000 T _sheap2
28000000 T _eheap2

With the PR it should be:

28000000 T _sheap2
28004000 T _eheap2

Issues/PRs references

riot-ci · 2023-07-24T10:30:28Z

Murdock results

✔️ PASSED

fdac7d4 cpu/stm32: fix ld script for SRAM4

Success	Failures	Total	Runtime
7906	0	7906	12m:08s

Artifacts

Documentation preview

benpicco

Thank you for spotting this!
The crashes still concern me, but they already happen in master 😬

benpicco · 2023-07-24T10:50:27Z

bors merge

gschorcht · 2023-07-24T11:00:57Z

The crashes still concern me, but they already happen in master 😬

It seems that malloc crashes when _sbrk_r returns NULL. This happens for the STM32U585 for any type of memory once the heap is exhausted. When you limit the used memory in tests/sys/malloc to MEM_MAX = heap_size - CHUNK_SIZE -8 so that the last call of _sbrk_r succeeds, everything works fine.

I will try to debug it later today.

bors · 2023-07-24T13:50:19Z

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19843: cpu/stm32/periph: add FMC/FSMC support for STM32 r=aabadie a=gschorcht ### Contribution description The PR provides a driver for STM32 FMC/FSMC peripherals. It supports: - NOR Flashes, - PSRAMs/SRAMs, - SDRAMs, and - Display Controllers with MCU 8-/16-bit parallel interface. NAND Flashes are not yet supported. To use the FMC/FSMC, the `periph_fmc` module has to be enabled. To keep required data structures and resulting code as small as possible, a couple of pseudomodules are defined that have to be used in addition to the `periph_fmc` module to enable supported features. These are: | Module | Feature | |:-----------------------|:----------------------------------------| | `periph_fmc_nor_sram` | enable NOR Flash and PSRAM/SRAM support | | `periph_fmc_sdram` | enable SDRAM support | | `periph_fmc_16bit` | enable 16-bit support | | `periph_fmc_32bit` | enable 32-bit support | The board has then to define - the corresponding features according to the connected external device, - the peripheral configuration of the FMC/FSMC of type `fmc_conf_t,` - the configuration of the FMC banks which describe the connected external devices. The PR includes the support for - `stm32f429i-disc1` with 8 MByte SDRAM - `stm32f746g-disco` with 16 MByte SDRAM - `stm32l496g-disco` with 1 MByte SRAM - `stm32f723e-disco` with 1 MByte SRAM. To use the RAM connected to the FMC as heap, the board defines `FMC_RAM_ADDR` and ` FMC_RAM_LEN`. For that purpose: - the linker symbols `_fmc_ram_addr` and `_fmc_ram_len` are set, - a memory region `fcmram` is added in linker script for the FMC RAM based on these `_fcm_ram_*` linker symbols - a section for the FMC RAM is defined in this memory region that defines the heap by setting `_sheap3` and `_eheap3` and - the number of heaps is set to 4 to use `_sheap3` and `_eheap3` even though `_sheap1` and `_eheap1` (the backup RAM) and `_sheap2` and `_eheap2` (SRAM4) are not present. Once the `drivers/st77xx` and `drivers/lcd` changes are merged, the display for boards like the `stm32l496g-disco` and `stm32f723e-disco` can also use the FMC peripheral. ~**NOTE**: The PR includes the fix in PR #19842 for now (commit 560fea1).~ ### Testing procedure 1. Use one of the boards above and flash `tests/driver/stm32_fmc`, for example: ``` BOARD=stm32f429i-disc1 make -j8 -C tests/drivers/stm32_fmc flash test ``` The test should succeed. **NOTE**: There is still a problem with `stm32f746g-disco`. It crashes with a hard-fault on accessing the upper 8 MByte of the 16 MByte. 2. Use the board above and flash `tests/sys/malloc`, for example: ``` USEMODULE=periph_fmc CFLAGS='-DCHUNK_SIZE=4096 -DDEBUG_ASSERT_VERBOSE' \ BOARD=stm32f429i-disc1 make -j8 -C tests/sys/malloc ``` The FMC RAM should be used for `malloc`. On `stm32f746g-disco` for example ``` ... Allocated 4096 Bytes at 0x2002d7c8, total 184672 Allocated 4096 Bytes at 0x2002e7e0, total 188776 Allocated 4096 Bytes at 0xd0000008, total 192880 Allocated 4096 Bytes at 0xd0001010, total 196984 Allocated 4096 Bytes at 0xd0002018, total 201088 ... Allocated 4096 Bytes at 0xd07fd6d0, total 8544520 Allocated 4096 Bytes at 0xd07fe6e8, total 8548624 Allocations count: 2083 ``` ### Issues/PRs references ~Depends on PR #19842~ Co-authored-by: Gunar Schorcht <[email protected]>

19843: cpu/stm32/periph: add FMC/FSMC support for STM32 r=aabadie a=gschorcht ### Contribution description The PR provides a driver for STM32 FMC/FSMC peripherals. It supports: - NOR Flashes, - PSRAMs/SRAMs, - SDRAMs, and - Display Controllers with MCU 8-/16-bit parallel interface. NAND Flashes are not yet supported. To use the FMC/FSMC, the `periph_fmc` module has to be enabled. To keep required data structures and resulting code as small as possible, a couple of pseudomodules are defined that have to be used in addition to the `periph_fmc` module to enable supported features. These are: | Module | Feature | |:-----------------------|:----------------------------------------| | `periph_fmc_nor_sram` | enable NOR Flash and PSRAM/SRAM support | | `periph_fmc_sdram` | enable SDRAM support | | `periph_fmc_16bit` | enable 16-bit support | | `periph_fmc_32bit` | enable 32-bit support | The board has then to define - the corresponding features according to the connected external device, - the peripheral configuration of the FMC/FSMC of type `fmc_conf_t,` - the configuration of the FMC banks which describe the connected external devices. The PR includes the support for - `stm32f429i-disc1` with 8 MByte SDRAM - `stm32f746g-disco` with 16 MByte SDRAM - `stm32l496g-disco` with 1 MByte SRAM - `stm32f723e-disco` with 1 MByte SRAM. To use the RAM connected to the FMC as heap, the board defines `FMC_RAM_ADDR` and ` FMC_RAM_LEN`. For that purpose: - the linker symbols `_fmc_ram_addr` and `_fmc_ram_len` are set, - a memory region `fcmram` is added in linker script for the FMC RAM based on these `_fcm_ram_*` linker symbols - a section for the FMC RAM is defined in this memory region that defines the heap by setting `_sheap3` and `_eheap3` and - the number of heaps is set to 4 to use `_sheap3` and `_eheap3` even though `_sheap1` and `_eheap1` (the backup RAM) and `_sheap2` and `_eheap2` (SRAM4) are not present. Once the `drivers/st77xx` and `drivers/lcd` changes are merged, the display for boards like the `stm32l496g-disco` and `stm32f723e-disco` can also use the FMC peripheral. ~**NOTE**: The PR includes the fix in PR #19842 for now (commit 560fea1).~ ### Testing procedure 1. Use one of the boards above and flash `tests/driver/stm32_fmc`, for example: ``` BOARD=stm32f429i-disc1 make -j8 -C tests/drivers/stm32_fmc flash test ``` The test should succeed. **NOTE**: There is still a problem with `stm32f746g-disco`. It crashes with a hard-fault on accessing the upper 8 MByte of the 16 MByte. 2. Use the board above and flash `tests/sys/malloc`, for example: ``` USEMODULE=periph_fmc CFLAGS='-DCHUNK_SIZE=4096 -DDEBUG_ASSERT_VERBOSE' \ BOARD=stm32f429i-disc1 make -j8 -C tests/sys/malloc ``` The FMC RAM should be used for `malloc`. On `stm32f746g-disco` for example ``` ... Allocated 4096 Bytes at 0x2002d7c8, total 184672 Allocated 4096 Bytes at 0x2002e7e0, total 188776 Allocated 4096 Bytes at 0xd0000008, total 192880 Allocated 4096 Bytes at 0xd0001010, total 196984 Allocated 4096 Bytes at 0xd0002018, total 201088 ... Allocated 4096 Bytes at 0xd07fd6d0, total 8544520 Allocated 4096 Bytes at 0xd07fe6e8, total 8548624 Allocations count: 2083 ``` ### Issues/PRs references ~Depends on PR #19842~ 19847: .github: drop test-on-ryot workflow r=aabadie a=aabadie Co-authored-by: Gunar Schorcht <[email protected]> Co-authored-by: Alexandre Abadie <[email protected]>

cpu/stm32: fix ld script for SRAM4

fdac7d4

gschorcht requested review from aabadie, fjmolinas, DipSwitch and vincent-d as code owners July 22, 2023 11:11

github-actions bot added Platform: ARM Platform: This PR/issue effects ARM-based platforms Area: cpu Area: CPU/MCU ports labels Jul 22, 2023

gschorcht added a commit to gschorcht/RIOT-Xtensa-ESP that referenced this pull request Jul 22, 2023

REMOVEME: ld script fix in PR RIOT-OS#19842

560fea1

gschorcht mentioned this pull request Jul 22, 2023

cpu/stm32/periph: add FMC/FSMC support for STM32 #19843

Merged

gschorcht requested a review from benpicco July 24, 2023 04:34

benpicco added the CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR label Jul 24, 2023

benpicco approved these changes Jul 24, 2023

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bors bot merged commit bff7452 into RIOT-OS:master Jul 24, 2023

gschorcht deleted the cpu/stm32/fix_ld_script branch September 10, 2023 11:18

MrKevinWeiss added this to the Release 2023.10 milestone Nov 17, 2023

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cpu/stm32: fix ld script for SRAM4 #19842

cpu/stm32: fix ld script for SRAM4 #19842

gschorcht commented Jul 22, 2023 •

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riot-ci commented Jul 24, 2023

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gschorcht commented Jul 24, 2023

bors bot commented Jul 24, 2023

cpu/stm32: fix ld script for SRAM4 #19842

cpu/stm32: fix ld script for SRAM4 #19842

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gschorcht commented Jul 22, 2023 • edited Loading

Contribution description

Testing procedure

Issues/PRs references

riot-ci commented Jul 24, 2023

Murdock results

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benpicco commented Jul 24, 2023

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gschorcht commented Jul 22, 2023 •

edited

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