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cpu/qn908x: use bitarithm_test_and_clear() & fix cb #18989

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merged 2 commits into from
Nov 28, 2022
Merged

cpu/qn908x: use bitarithm_test_and_clear() & fix cb #18989

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c950286
cpu/qn909x/periph_timer: make clangd happy
maribu Nov 28, 2022
0d85356
cpu/qn908x: use bitarithm_test_and_clear() & fix cb
maribu Nov 28, 2022
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28 changes: 15 additions & 13 deletions cpu/qn908x/periph/timer.c
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Original file line number Diff line number Diff line change
Expand Up @@ -25,10 +25,11 @@

#include <stdlib.h>

#include "cpu.h"
#include "bitarithm.h"
#include "board.h"
#include "periph_conf.h"
#include "cpu.h"
#include "periph/timer.h"
#include "periph_conf.h"

#include "vendor/drivers/fsl_clock.h"

Expand Down Expand Up @@ -66,9 +67,9 @@ static const clock_ip_name_t ctimers_clocks[FSL_FEATURE_SOC_CTIMER_COUNT] =
#error "ERROR in board timer configuration: too many timers defined"
#endif

int timer_init(tim_t tim, unsigned long freq, timer_cb_t cb, void *arg)
int timer_init(tim_t tim, uint32_t freq, timer_cb_t cb, void *arg)
{
DEBUG("timer_init(%u, %lu)\n", tim, freq);
DEBUG("timer_init(%u, %" PRIu32 ")\n", tim, freq);
if (tim >= TIMER_NUMOF) {
return -1;
}
Expand All @@ -84,7 +85,7 @@ int timer_init(tim_t tim, unsigned long freq, timer_cb_t cb, void *arg)
uint32_t core_freq = CLOCK_GetFreq(kCLOCK_ApbClk);
uint32_t prescale = (core_freq + freq / 2) / freq - 1;
if (prescale == (uint32_t)(-1)) {
DEBUG("timer_init: Frequency %lu is too fast for core_freq=%lu",
DEBUG("timer_init: Frequency %" PRIu32 " is too fast for core_freq=%" PRIu32,
freq, core_freq);
return -1;
}
Expand Down Expand Up @@ -144,14 +145,15 @@ static inline void isr_ctimer_n(CTIMER_Type *dev, uint32_t ctimer_num)
{
DEBUG("isr_ctimer_%" PRIu32 " flags=0x%" PRIx32 "\n",
ctimer_num, dev->IR);
for (uint32_t i = 0; i < TIMER_CHANNELS; i++) {
if (dev->IR & (1u << i)) {
/* Note: setting the bit to 1 in the flag register will clear the
* bit. */
dev->IR = 1u << i;
dev->MCR &= ~(CTIMER_MCR_MR0I_MASK << (i * 3));
isr_ctx[ctimer_num].cb(isr_ctx[ctimer_num].arg, 0);
}
unsigned state = dev->IR & ((1 << TIMER_CHANNELS) - 1);
while (state) {
uint8_t channel;
state = bitarithm_test_and_clear(state, &channel);
/* Note: setting the bit to 1 in the flag register will clear the
* bit. */
dev->IR = 1u << channel;
dev->MCR &= ~(CTIMER_MCR_MR0I_MASK << (channel * 3));
isr_ctx[ctimer_num].cb(isr_ctx[ctimer_num].arg, channel);
}
cortexm_isr_end();
}
Expand Down