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cpu/stm32: fix periph_dma #18711

Merged
merged 3 commits into from
Oct 27, 2022
Merged

Commits on Oct 26, 2022

  1. cpu/stm32/periph/dma: fix DMA2 on STMF3 families

    As it was, the calculation of DMA2's IRQ number was inccrorect for some
    STM families. The implmentation alocates streams numbers 0 to 7 for the
    first DMA controller and 8 and up for the second DMA controller. This
    offset of +8 was not accounted for when IRQ's of the second DMA
    controller was calculated. This patch corrects this.
    Enoch247 committed Oct 26, 2022
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  2. cpu/stm32/periph/dma: fix dma_resume

    As implmented, dma_resume assumed that transfers widths were 1 byte and
    that the memory address incrmenting was always on and periphial address
    incrementing always off. This resulted in memory corruption anytime
    these assumptions were not true and a dma was resumed. The DMA module
    allows intitiating transfers that did not meet these assumption.
    
    This patch adds proper handling inside dma_resume to safely resume any
    transfer. Clearifications and errors are added/fixed in the module's
    header file. Also, a few constants are removed from the gobal namespace.
    Enoch247 committed Oct 26, 2022
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  3. cpu/stm32/periph/dma: make dma_prepare() generic

    This patch makes dma_prepare() handle register names a bit more
    generically.
    Enoch247 committed Oct 26, 2022
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