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Merge pull request #20479 from Enoch247/simplify-stm32-gpio-code
cpu/stm32/periph/gpio: simplify condition code
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Original file line number | Diff line number | Diff line change |
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@@ -22,6 +22,7 @@ | |
* @author Alexandre Abadie <[email protected]> | ||
* @author Katja Kirstein <[email protected]> | ||
* @author Vincent Dupont <[email protected]> | ||
* @author Joshua DeWeese <[email protected]> | ||
* | ||
* @} | ||
*/ | ||
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@@ -98,31 +99,30 @@ static inline int _pin_num(gpio_t pin) | |
static inline void port_init_clock(GPIO_TypeDef *port, gpio_t pin) | ||
{ | ||
(void)port; /* <-- Only used for when port G requires special handling */ | ||
#if defined(CPU_FAM_STM32F0) || defined (CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L1) | ||
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||
#if defined(RCC_AHBENR_GPIOAEN) | ||
periph_clk_en(AHB, (RCC_AHBENR_GPIOAEN << _port_num(pin))); | ||
#elif defined (CPU_FAM_STM32L0) || defined(CPU_FAM_STM32G0) || \ | ||
defined(CPU_FAM_STM32C0) | ||
periph_clk_en(IOP, (RCC_IOPENR_GPIOAEN << _port_num(pin))); | ||
#elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \ | ||
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5) || \ | ||
defined(CPU_FAM_STM32U5) || defined (CPU_FAM_STM32WL) | ||
#if defined(CPU_FAM_STM32U5) | ||
#elif defined(RCC_AHB1ENR_GPIOAEN) | ||
periph_clk_en(AHB1, (RCC_AHB1ENR_GPIOAEN << _port_num(pin))); | ||
#elif defined(RCC_AHB2ENR_GPIOAEN) | ||
periph_clk_en(AHB2, (RCC_AHB2ENR_GPIOAEN << _port_num(pin))); | ||
#elif defined(RCC_AHB2ENR1_GPIOAEN) | ||
periph_clk_en(AHB2, (RCC_AHB2ENR1_GPIOAEN << _port_num(pin))); | ||
#elif defined(RCC_MC_AHB4ENSETR_GPIOAEN) | ||
periph_clk_en(AHB4, (RCC_MC_AHB4ENSETR_GPIOAEN << _port_num(pin))); | ||
#elif defined (RCC_IOPENR_GPIOAEN) | ||
periph_clk_en(IOP, (RCC_IOPENR_GPIOAEN << _port_num(pin))); | ||
#else | ||
periph_clk_en(AHB2, (RCC_AHB2ENR_GPIOAEN << _port_num(pin))); | ||
#error "GPIO periph clock undefined" | ||
#endif | ||
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||
#ifdef PWR_CR2_IOSV | ||
if (port == GPIOG) { | ||
/* Port G requires external power supply */ | ||
periph_clk_en(APB1, RCC_APB1ENR1_PWREN); | ||
PWR->CR2 |= PWR_CR2_IOSV; | ||
} | ||
#endif /* PWR_CR2_IOSV */ | ||
#elif defined(CPU_FAM_STM32MP1) | ||
periph_clk_en(AHB4, (RCC_MC_AHB4ENSETR_GPIOAEN << _port_num(pin))); | ||
#else | ||
periph_clk_en(AHB1, (RCC_AHB1ENR_GPIOAEN << _port_num(pin))); | ||
#endif | ||
} | ||
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||
static inline void set_mode(GPIO_TypeDef *port, int pin_num, unsigned mode) | ||
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@@ -172,22 +172,22 @@ void gpio_init_analog(gpio_t pin) | |
{ | ||
/* enable clock, needed as this function can be used without calling | ||
* gpio_init first */ | ||
#if defined(CPU_FAM_STM32F0) || defined (CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L1) | ||
#if defined(RCC_AHBENR_GPIOAEN) | ||
periph_clk_en(AHB, (RCC_AHBENR_GPIOAEN << _port_num(pin))); | ||
#elif defined (CPU_FAM_STM32L0) || defined(CPU_FAM_STM32G0) || \ | ||
defined(CPU_FAM_STM32C0) | ||
periph_clk_en(IOP, (RCC_IOPENR_GPIOAEN << _port_num(pin))); | ||
#elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \ | ||
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5) || \ | ||
defined (CPU_FAM_STM32WL) | ||
#elif defined(RCC_AHB1ENR_GPIOAEN) | ||
periph_clk_en(AHB1, (RCC_AHB1ENR_GPIOAEN << _port_num(pin))); | ||
#elif defined(RCC_AHB2ENR_GPIOAEN) | ||
periph_clk_en(AHB2, (RCC_AHB2ENR_GPIOAEN << _port_num(pin))); | ||
#elif defined(CPU_FAM_STM32U5) | ||
#elif defined(RCC_AHB2ENR1_GPIOAEN) | ||
periph_clk_en(AHB2, (RCC_AHB2ENR1_GPIOAEN << _port_num(pin))); | ||
#elif defined(CPU_FAM_STM32MP1) | ||
#elif defined(RCC_MC_AHB4ENSETR_GPIOAEN) | ||
periph_clk_en(AHB4, (RCC_MC_AHB4ENSETR_GPIOAEN << _port_num(pin))); | ||
#elif defined (RCC_IOPENR_GPIOAEN) | ||
periph_clk_en(IOP, (RCC_IOPENR_GPIOAEN << _port_num(pin))); | ||
#else | ||
periph_clk_en(AHB1, (RCC_AHB1ENR_GPIOAEN << _port_num(pin))); | ||
#error "GPIO periph clock undefined" | ||
#endif | ||
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||
/* set to analog mode, PUPD has to be 0b00 */ | ||
_port(pin)->MODER |= (0x3 << (2 * _pin_num(pin))); | ||
_port(pin)->PUPDR &= ~(0x3 << (2 * _pin_num(pin))); | ||
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