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kinetis: Use bitband.h macros
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Joakim Nohlgård committed May 2, 2017
1 parent c99b37b commit a5e2d80
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Showing 12 changed files with 65 additions and 121 deletions.
6 changes: 4 additions & 2 deletions boards/frdm-k64f/include/periph_conf.h
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Original file line number Diff line number Diff line change
Expand Up @@ -68,10 +68,11 @@ extern "C"
#define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))

#define PIT_BASECLOCK (CLOCK_BUSCLOCK)
#define PIT_CLOCKGATE (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_PIT_SHIFT))
#define PIT_CLKEN() (bit_set32(&SIM->SCGC6, SIM_SCGC6_PIT_SHIFT))
#define PIT_ISR_0 isr_pit1
#define PIT_ISR_1 isr_pit3
#define LPTMR_ISR_0 isr_lptmr0
#define LPTMR_CLKEN() (bit_set32(&SIM->SCGC5, SIM_SCGC5_LPTMR_SHIFT))

/** @} */

Expand All @@ -82,13 +83,14 @@ extern "C"
static const uart_conf_t uart_config[] = {
{
.dev = UART0,
.clken = (volatile uint32_t*)(BITBAND_REGADDR(SIM->SCGC4, SIM_SCGC4_UART0_SHIFT)),
.freq = CLOCK_CORECLOCK,
.pin_rx = GPIO_PIN(PORT_B, 16),
.pin_tx = GPIO_PIN(PORT_B, 17),
.pcr_rx = PORT_PCR_MUX(3),
.pcr_tx = PORT_PCR_MUX(3),
.irqn = UART0_RX_TX_IRQn,
.scgc_addr = &SIM->SCGC4,
.scgc_bit = SIM_SCGC4_UART0_SHIFT,
},
};

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12 changes: 7 additions & 5 deletions boards/mulle/include/periph_conf.h
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Original file line number Diff line number Diff line change
Expand Up @@ -78,17 +78,17 @@ extern "C"
#define LPTMR_CONFIG { \
{ \
.dev = LPTMR0, \
.clk_gate = (uint32_t volatile *)BITBAND_REGADDR(SIM->SCGC5, SIM_SCGC5_LPTIMER_SHIFT), \
.index = 0, \
.irqn = LPTMR0_IRQn, \
} \
}
#define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))

#define PIT_BASECLOCK (CLOCK_BUSCLOCK)
#define PIT_CLOCKGATE (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_PIT_SHIFT))
#define PIT_CLKEN() (bit_set32(&SIM->SCGC6, SIM_SCGC6_PIT_SHIFT))
#define PIT_ISR_0 isr_pit1
#define PIT_ISR_1 isr_pit3
#define LPTMR_ISR_0 isr_lptmr0
#define LPTMR_CLKEN() (bit_set32(&SIM->SCGC5, SIM_SCGC5_LPTMR_SHIFT))

/** @} */

Expand All @@ -99,23 +99,25 @@ extern "C"
static const uart_conf_t uart_config[] = {
{
.dev = UART0,
.clken = (volatile uint32_t*)(BITBAND_REGADDR(SIM->SCGC4, SIM_SCGC4_UART0_SHIFT)),
.freq = CLOCK_CORECLOCK,
.pin_rx = GPIO_PIN(PORT_A, 14),
.pin_tx = GPIO_PIN(PORT_A, 15),
.pcr_rx = PORT_PCR_MUX(3),
.pcr_tx = PORT_PCR_MUX(3),
.irqn = UART0_RX_TX_IRQn,
.scgc_addr = &SIM->SCGC4,
.scgc_bit = SIM_SCGC4_UART0_SHIFT,
},
{
.dev = UART1,
.clken = (volatile uint32_t*)(BITBAND_REGADDR(SIM->SCGC4, SIM_SCGC4_UART1_SHIFT)),
.freq = CLOCK_CORECLOCK,
.pin_rx = GPIO_PIN(PORT_C, 3),
.pin_tx = GPIO_PIN(PORT_C, 4),
.pcr_rx = PORT_PCR_MUX(3),
.pcr_tx = PORT_PCR_MUX(3),
.irqn = UART1_RX_TX_IRQn,
.scgc_addr = &SIM->SCGC4,
.scgc_bit = SIM_SCGC4_UART1_SHIFT,
},
};

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9 changes: 6 additions & 3 deletions boards/pba-d-01-kw2x/include/periph_conf.h
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Original file line number Diff line number Diff line change
Expand Up @@ -70,10 +70,11 @@ extern "C"
#define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))

#define PIT_BASECLOCK (CLOCK_BUSCLOCK)
#define PIT_CLOCKGATE (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_PIT_SHIFT))
#define PIT_CLKEN() (bit_set32(&SIM->SCGC6, SIM_SCGC6_PIT_SHIFT))
#define PIT_ISR_0 isr_pit1
#define PIT_ISR_1 isr_pit3
#define LPTMR_ISR_0 isr_lptmr0
#define LPTMR_CLKEN() (bit_set32(&SIM->SCGC5, SIM_SCGC5_LPTMR_SHIFT))

/** @} */

Expand All @@ -84,23 +85,25 @@ extern "C"
static const uart_conf_t uart_config[] = {
{
.dev = UART2,
.clken = (volatile uint32_t*)(BITBAND_REGADDR(SIM->SCGC4, SIM_SCGC4_UART2_SHIFT)),
.freq = CLOCK_BUSCLOCK,
.pin_rx = GPIO_PIN(PORT_D, 2),
.pin_tx = GPIO_PIN(PORT_D, 3),
.pcr_rx = PORT_PCR_MUX(3),
.pcr_tx = PORT_PCR_MUX(3),
.irqn = UART2_RX_TX_IRQn,
.scgc_addr = &SIM->SCGC4,
.scgc_bit = SIM_SCGC4_UART2_SHIFT,
},
{
.dev = UART0,
.clken = (volatile uint32_t*)(BITBAND_REGADDR(SIM->SCGC4, SIM_SCGC4_UART0_SHIFT)),
.freq = CLOCK_CORECLOCK,
.pin_rx = GPIO_PIN(PORT_D, 6),
.pin_tx = GPIO_PIN(PORT_D, 7),
.pcr_rx = PORT_PCR_MUX(3),
.pcr_tx = PORT_PCR_MUX(3),
.irqn = UART0_RX_TX_IRQn,
.scgc_addr = &SIM->SCGC4,
.scgc_bit = SIM_SCGC4_UART0_SHIFT,
}
};

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63 changes: 7 additions & 56 deletions cpu/k60/include/cpu_conf.h
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Original file line number Diff line number Diff line change
Expand Up @@ -68,29 +68,19 @@ extern "C"
#define PIN_INTERRUPT_EDGE 0b1011
/** @} */

/** @name PORT module clock gates */
/** @{ */
#define PORTA_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTA_SHIFT))
#define PORTB_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT))
#define PORTC_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT))
#define PORTD_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT))
#define PORTE_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT))
/** @} */

/**
* @name Clock settings for the LPTMR0 timer
* @{
*/
#define LPTIMER_DEV (LPTMR0) /**< LPTIMER hardware module */
#define LPTIMER_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_LPTIMER_SHIFT) = 1) /**< Enable LPTMR0 clock gate */
#define LPTIMER_CLKDIS() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_LPTIMER_SHIFT) = 0) /**< Disable LPTMR0 clock gate */
#define LPTIMER_CLKSRC_MCGIRCLK 0 /**< internal reference clock (4MHz) */
#define LPTIMER_CLKSRC_LPO 1 /**< PMC 1kHz output */
#define LPTIMER_CLKSRC_ERCLK32K 2 /**< RTC clock 32768Hz */
#define LPTIMER_CLKSRC_OSCERCLK 3 /**< system oscillator output, clock from RF-Part */
#define LPTIMER_DEV (LPTMR0) /**< LPTIMER hardware module */
#define LPTIMER_CLKEN() (bit_set32(&SIM->SCGC5, SIM_SCGC5_LPTMR_SHIFT)) /**< Enable LPTMR0 clock gate */
#define LPTIMER_CLKSRC_MCGIRCLK 0 /**< internal reference clock (4MHz) */
#define LPTIMER_CLKSRC_LPO 1 /**< PMC 1kHz output */
#define LPTIMER_CLKSRC_ERCLK32K 2 /**< RTC clock 32768Hz */
#define LPTIMER_CLKSRC_OSCERCLK 3 /**< system oscillator output */

#ifndef LPTIMER_CLKSRC
#define LPTIMER_CLKSRC LPTIMER_CLKSRC_ERCLK32K /**< default clock source */
#define LPTIMER_CLKSRC LPTIMER_CLKSRC_ERCLK32K /**< default clock source */
#endif

#if (LPTIMER_CLKSRC == LPTIMER_CLKSRC_MCGIRCLK)
Expand Down Expand Up @@ -199,45 +189,6 @@ typedef enum llwu_wakeup_pin {

/** @} */

/**
* @name Bit band macros
* @{
*/
/* Generic bitband conversion routine */
/** @brief Convert bit-band region address and bit number to bit-band alias address
*
* @param[in] addr base address in non-bit-banded memory
* @param[in] bit bit number within the word
*
* @return Address of the bit within the bit-band memory region
*/
#define BITBAND_ADDR(addr, bit) ((((uint32_t) (addr)) & 0xF0000000u) + 0x2000000 + ((((uint32_t) (addr)) & 0xFFFFF) << 5) + ((bit) << 2))

/**
* @brief Bitband 32 bit access to variable stored in SRAM_U
*
* @note SRAM_L is not bit band aliased on the K60, only SRAM_U (0x20000000 and up)
* @note var must be declared 'volatile'
*/
#define BITBAND_VAR32(var, bit) (*((uint32_t volatile*) BITBAND_ADDR(&(var), (bit))))

/**
* @brief Bitband 16 bit access to variable stored in SRAM_U
*
* @note SRAM_L is not bit band aliased on the K60, only SRAM_U (0x20000000 and up)
* @note var must be declared 'volatile'
*/
#define BITBAND_VAR16(var, bit) (*((uint16_t volatile*) BITBAND_ADDR(&(var), (bit))))

/**
* @brief Bitband 8 bit access to variable stored in SRAM_U
*
* @note SRAM_L is not bit band aliased on the K60, only SRAM_U (0x20000000 and up)
* @note var must be declared 'volatile'
*/
#define BITBAND_VAR8(var, bit) (*((uint8_t volatile*) BITBAND_ADDR(&(var), (bit))))

/** @} */
#ifdef __cplusplus
}
#endif
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15 changes: 2 additions & 13 deletions cpu/k64f/include/cpu_conf.h
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Expand Up @@ -62,22 +62,11 @@ extern "C"
#define PIN_INTERRUPT_EDGE 0b1011
/** @} */

/** @name PORT module clock gates */
/** @{ */
#define PORTA_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTA_SHIFT))
#define PORTB_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT))
#define PORTC_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT))
#define PORTD_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT))
#define PORTE_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT))
/** @} */

/**
* @brief MCU specific Low Power Timer settings.
*/
#define LPTIMER_CLKSRC LPTIMER_CLKSRC_LPO
#define LPTIMER_DEV (LPTMR0) /**< LPTIMER hardware module */
#define LPTIMER_CLKEN() (SIM->SCGC5 |= SIM_SCGC5_LPTMR_MASK) /**< Enable LPTMR0 clock gate */
#define LPTIMER_CLKDIS() (SIM->SCGC5 &= ~SIM_SCGC5_PTMR_MASK) /**< Disable LPTMR0 clock gate */
#define LPTIMER_DEV (LPTMR0) /**< LPTIMER hardware module */
#define LPTIMER_CLKEN() (bit_set32(&SIM->SCGC5, SIM_SCGC5_LPTMR_SHIFT)) /**< Enable LPTMR0 clock gate */

#ifdef __cplusplus
}
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23 changes: 11 additions & 12 deletions cpu/kinetis_common/include/periph_cpu.h
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Original file line number Diff line number Diff line change
Expand Up @@ -249,10 +249,8 @@ typedef struct {
typedef struct {
/** LPTMR device base pointer */
LPTMR_Type *dev;
/** Pointer to module clock gate bit in bitband region, use BITBAND_REGADDR() */
uint32_t volatile *clk_gate;
/** LPTMR device index */
uint8_t index;
/** IRQn interrupt number */
uint8_t irqn;
} lptmr_conf_t;

/**
Expand Down Expand Up @@ -302,14 +300,15 @@ enum {
* @brief UART module configuration options
*/
typedef struct {
UART_Type *dev; /**< Pointer to module hardware registers */
volatile uint32_t *clken; /**< Clock enable bitband register address */
uint32_t freq; /**< Module clock frequency, usually CLOCK_CORECLOCK or CLOCK_BUSCLOCK */
gpio_t pin_rx; /**< RX pin, GPIO_UNDEF disables RX */
gpio_t pin_tx; /**< TX pin */
uint32_t pcr_rx; /**< Pin configuration register bits for RX */
uint32_t pcr_tx; /**< Pin configuration register bits for TX */
IRQn_Type irqn; /**< IRQ number for this module */
UART_Type *dev; /**< Pointer to module hardware registers */
uint32_t freq; /**< Module clock frequency, usually CLOCK_CORECLOCK or CLOCK_BUSCLOCK */
gpio_t pin_rx; /**< RX pin, GPIO_UNDEF disables RX */
gpio_t pin_tx; /**< TX pin */
uint32_t pcr_rx; /**< Pin configuration register bits for RX */
uint32_t pcr_tx; /**< Pin configuration register bits for TX */
IRQn_Type irqn; /**< IRQ number for this module */
volatile uint32_t *scgc_addr; /**< Clock enable register, in SIM module */
uint8_t scgc_bit; /**< Clock enable bit, within the register */
} uart_conf_t;

/**
Expand Down
8 changes: 4 additions & 4 deletions cpu/kinetis_common/periph/adc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -65,11 +65,11 @@ static inline int dev_num(adc_t line)
static inline void prep(adc_t line)
{
if (dev(line) == ADC0) {
BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_ADC0_SHIFT) = 1;
bit_set32(&SIM->SCGC6, SIM_SCGC6_ADC0_SHIFT);
}
#ifdef ADC1
else {
BITBAND_REG32(SIM->SCGC3, SIM_SCGC3_ADC1_SHIFT) = 1;
bit_set32(&SIM->SCGC3, SIM_SCGC3_ADC1_SHIFT);
}
#endif
mutex_lock(&locks[dev_num(line)]);
Expand All @@ -78,11 +78,11 @@ static inline void prep(adc_t line)
static inline void done(adc_t line)
{
if (dev(line) == ADC0) {
BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_ADC0_SHIFT) = 0;
bit_clear32(&SIM->SCGC6, SIM_SCGC6_ADC0_SHIFT);
}
#ifdef ADC1
else {
BITBAND_REG32(SIM->SCGC3, SIM_SCGC3_ADC1_SHIFT) = 0;
bit_clear32(&SIM->SCGC3, SIM_SCGC3_ADC1_SHIFT);
}
#endif
mutex_unlock(&locks[dev_num(line)]);
Expand Down
7 changes: 6 additions & 1 deletion cpu/kinetis_common/periph/dac.c
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Original file line number Diff line number Diff line change
Expand Up @@ -84,7 +84,12 @@ static inline void _dac_set_power(dac_t line, uint8_t value)

dac = dac_config[line].dev;

BITBAND_REG8(dac->C0, DAC_C0_DACEN_SHIFT) = value;
if (value) {
bit_set8(&dac->C0, DAC_C0_DACEN_SHIFT);
}
else {
bit_clear8(&dac->C0, DAC_C0_DACEN_SHIFT);
}
}

void dac_poweron(dac_t line)
Expand Down
2 changes: 1 addition & 1 deletion cpu/kinetis_common/periph/gpio.c
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Original file line number Diff line number Diff line change
Expand Up @@ -129,7 +129,7 @@ static inline int pin_num(gpio_t pin)

static inline void clk_en(gpio_t pin)
{
BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTA_SHIFT + port_num(pin)) = 1;
bit_set32(&SIM->SCGC5, SIM_SCGC5_PORTA_SHIFT + port_num(pin));
}

/**
Expand Down
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