Merge #19760 #19946 #19956 #19957

19760: cpu/sam0_common/periph: add low-level SDMMC peripheral driver for SDHC r=benpicco a=gschorcht ### Contribution description This PR implements the low-level SDIO/SDMMC peripheral driver for SAM0 SDHC according to the definition in #19539. ### Testing procedure ``` BOARD=same54-xpro make -C tests/drivers/sdmmc ``` ``` BOARD=same54-xpro make -C tests/sys/vfs_default ``` ### Issues/PRs references ~Depends on PR #19539~ Depends on PR #19899 19946: posix_sockets.c: Fix 2 byte int compilation errors r=benpicco a=mrdeep1 19956: cpu/esp32: fix heap definition for ESP32-S2 and ESP32-S3 r=benpicco a=gschorcht ### Contribution description For ESP32-S2 and ESP32-S3 the symbol `_heap_end` must not be used as `_eheap` for the newlibc `malloc` and function `sbrk`. `_heap_end` is used by the ESP-IDF heap implementation `esp-idf-heap` and points to the highest possible address (0x40000000) that could be used for the heap in ESP-IDF. It doesn't point to the top address of the unused SRAM area that can be used in newlibc `malloc` and function `sbrk`. Instead, the origin and the length of `dram0_0_seg` must be used to calculate the end of the heap `_eheap`. The problem only occurs for the newlibc `malloc` when the `sbrk` function is used but not for the ESP-IDF heap implementation `esp_idf_heap`. ### Testing procedure Use any ESP32-S2 or ESP32-S3 board and flash `tests/sys/malloc`, e.g. ``` CFLAGS='-DCHUNK_SIZE=16384' USEMODULE='stdio_uart' BOARD=esp32s3-pros3 make -j8 -C tests/sys/malloc flash ``` Without the PR the `nm` command will give the wrong address ``` nm -s tests/sys/malloc/bin/esp32s3-pros3/tests_malloc.elf | grep _eheap 40000000 A _eheap ``` The test will stuck, i.e. the allocation of memory stops when the top of unused SRAM is reached and the board restarts when the watchdog timer expires. With the PR it should work as expected ``` Help: Press s to start test, r to print it is ready START main(): This is RIOT! (Version: 2023.10-devel-309-g4669e) calloc(zu, zu) = 0x10000000 CHUNK_SIZE: 16384 NUMBER_OF_TESTS: 3 Allocated 16384 Bytes at 0x3fc8c4b0, total 16384 ... Allocated 16384 Bytes at 0x3fcec6f0, total 409792 ESP-ROM:esp32s3-20210327 Build:Mar 27 2021 rst:0x7 (TG0WDT_SYS_RST),boot:0x8 (SPI_FAST_FLASH_BOOT) Saved PC:0x403763e3 ``` With this PR the `nm` command should give a address in unused SRAM address space ``` nm -s tests/sys/malloc/bin/esp32s3-pros3/tests_malloc.elf | grep _eheap 3fcca000 A _eheap ``` and the test should pass. ### Issues/PRs references 19957: cpu/esp32: fix Octal SPI RAM for ESP32-S3 r=benpicco a=gschorcht ### Contribution description This PR fixes Octal SPI RAM handling for ESP32-S3. Functions that are used during the initialization of the Octal SPI RAM must reside in IRAM instead of Flash. Otherwise, the system stucks during boot once the Octal SPI RAM is enabled. The reason is that the Flash is not available during the initialization of the Octal SPI RAM and the functions that are called during that initialization can't be accessed in Flash. As a result the call of such a function leads to code that is messed up and the system crashes. The PR also includes the documentation fixe for the `esp32s3-box`. It also includes a small documentation fix regarding the SPI RAM for the `esp32s3-pros3` board. ### Testing procedure Use a board that has Octal SPI RAM and flash `tests/sys/malloc`, e.g.: ``` CFLAGS='-DCHUNK_SIZE=16384' USEMODULE='stdio_uart esp_spi_ram esp_log_startup' \ BOARD=esp32s3-box make -C tests/sys/malloc ``` Without the PR, the system stuck during boot once the information for the Octal SPI RAM is print ``` ESP-ROM:esp32s3-20210327 ... I (133) boot: Loaded app from partition at offset 0x10000 I (134) boot: Disabling RNG early entropy source... vendor id : 0x0d (AP) dev id : 0x02 (generation 3) density : 0x03 (64 Mbit) good-die : 0x01 (Pass) Latency : 0x01 (Fixed) VCC : 0x01 (3V) SRF : 0x01 (Fast Refresh) BurstType : 0x01 (Hybrid Wrap) BurstLen : 0x01 (32 Byte) Readlatency : 0x02 (10 cycles@Fixed) DriveStrength: 0x00 (1/1) ``` and the board restarts when the watchdog timer expires. With this PR, the system starts as expected. ``` ESP-ROM:esp32s3-20210327 ... I (132) boot: Loaded app from partition at offset 0x10000 I (133) boot: Disabling RNG early entropy source... vendor id : 0x0d (AP) dev id : 0x02 (generation 3) density : 0x03 (64 Mbit) good-die : 0x01 (Pass) Latency : 0x01 (Fixed) VCC : 0x01 (3V) SRF : 0x01 (Fast Refresh) BurstType : 0x01 (Hybrid Wrap) BurstLen : 0x01 (32 Byte) Readlatency : 0x02 (10 cycles@Fixed) DriveStrength: 0x00 (1/1) Found 64MBit SPI RAM device SPI RAM mode: sram 40m PSRAM initialized, cache is in normal (1-core) mode. Pro cpu up. Single core mode SPI SRAM memory test OK Initializing. RAM available for dynamic allocation: At 3FC8C150 len 00053EB0 (335 KiB): D/IRAM At 3FCE0000 len 0000EE34 (59 KiB): STACK/DRAM At 3FCF0000 len 00008000 (32 KiB): DRAM Starting ESP32x with ID: f412fafd0f8c ESP-IDF SDK Version v4.4.1 Current clocks in Hz: CPU=80000000 APB=80000000 XTAL=40000000 SLOW=150000 PRO cpu is up (single core mode, only PRO cpu is used) PRO cpu starts user code Adding pool of 8192K of external SPI memory to heap allocator Used clocks in Hz: CPU=80000000 APB=80000000 XTAL=40000000 FAST=8000000 SLOW=150000 XTAL calibration value: 3643448 Heap free: 8754851 bytes Board configuration: UART_DEV(0) txd=43 rxd=44 LED pins=[ ] BUTTONS pins=[ 0 ] Starting RIOT kernel on PRO cpu Help: Press s to start test, r to print it is ready ``` ### Issues/PRs references Co-authored-by: Gunar Schorcht <[email protected]> Co-authored-by: Jon Shallow <[email protected]>
RIOT-OS · Sep 29, 2023 · 149cee4 · 149cee4
5 parents 6a826fa + ca44651 + ed64f06 + 3a40e20 + cb88b86
commit 149cee4
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diff --git a/boards/esp32s3-box/doc.txt b/boards/esp32s3-box/doc.txt
@@ -37,7 +37,7 @@ The ESP32-S3-Box has following main features:
 |:--------------------------------------------|:-------:|
 | ESP32-S3 SoC                                | yes     |
 | 16 MB Flash                                 | yes     |
-| 8 MB QSPI RAM                               | yes     |
+| 8 MB Octal SPI RAM                          | yes     |
 | 2.4\" LCD Display 320 x 240 with ILI9342C   | yes     |
 | Capacitive Touch Panel                      | no      |
 | Dual Microphone ES7210                      | no      |
@@ -104,7 +104,7 @@ UART_DEV(0) RxD | GPIO44 | PMOD2 | \ref esp32_uart_interfaces "UART interfaces"
 The following figures show the pinouts as configured by default board
 definition.
 
-@image html https://raw.githubusercontent.com/espressif/esp-box/master/docs/_static/_get_started_static/hardware_pmod.png "ESP32-S3-BoxC-1 Pinout" width=900px
+@image html https://raw.githubusercontent.com/espressif/esp-box/master/docs/_static/previous_get_started_fig/hardware_pmod.png "ESP32-S3-BoxC-1 Pinout" width=900px
 
 The corresponding schematics can be found:
 

diff --git a/boards/esp32s3-pros3/doc.txt b/boards/esp32s3-pros3/doc.txt
@@ -33,7 +33,7 @@ The main features of the board are:
 
 - ESP32-S3 SoC with 2.4 GHz WiFi 802.11b/g/n and Bluetooth5, BLE
 - 16 MByte Flash
-- 4 MByte SPI RAM
+- 8 MByte QSPI RAM
 - RGB LED WS2812B
 - Native USB and USB Serial JTAG
 - LiPo Battery Charging and PicoBlade connector

diff --git a/boards/same54-xpro/Kconfig b/boards/same54-xpro/Kconfig
@@ -18,6 +18,7 @@ config BOARD_SAME54_XPRO
     select HAS_PERIPH_RTC
     select HAS_PERIPH_RTT
     select HAS_PERIPH_PWM
+    select HAS_PERIPH_SDMMC
     select HAS_PERIPH_SPI
     select HAS_PERIPH_TIMER
     select HAS_PERIPH_UART
@@ -31,6 +32,7 @@ config BOARD_SAME54_XPRO
     select HAVE_SAM0_ETH
     select HAVE_SAM0_SDHC
     select HAVE_MTD_AT24CXXX
+    select HAVE_MTD_SDMMC_DEFAULT
 
     # This specific board requires SPI_ON_QSPI for the MTD_SPI_NOR
     select MODULE_PERIPH_SPI_ON_QSPI if MODULE_MTD_SPI_NOR
diff --git a/boards/same54-xpro/Makefile.dep b/boards/same54-xpro/Makefile.dep
@@ -10,7 +10,11 @@ ifneq (,$(filter mtd,$(USEMODULE)))
   FEATURES_REQUIRED += periph_spi_on_qspi
   USEMODULE += mtd_spi_nor
   USEMODULE += mtd_at24cxxx at24mac
-  USEMODULE += sam0_sdhc
+  ifeq (,$(filter sam0_sdhc,$(USEMODULE)))
+    # during a transition period it is possible to use the `sam0_sdhc` MTD
+    # driver instead of the SD/MMC MTD driver
+    USEMODULE += mtd_sdmmc_default
+  endif
 endif
 
 # enables sam0_eth as default network device

diff --git a/boards/same54-xpro/Makefile.features b/boards/same54-xpro/Makefile.features
@@ -8,6 +8,7 @@ FEATURES_PROVIDED += periph_i2c
 FEATURES_PROVIDED += periph_rtc
 FEATURES_PROVIDED += periph_rtt
 FEATURES_PROVIDED += periph_pwm
+FEATURES_PROVIDED += periph_sdmmc
 FEATURES_PROVIDED += periph_spi
 FEATURES_PROVIDED += periph_timer
 FEATURES_PROVIDED += periph_uart

diff --git a/boards/same54-xpro/include/board.h b/boards/same54-xpro/include/board.h
@@ -76,6 +76,8 @@ extern mtd_dev_t *mtd0, *mtd1, *mtd2;
 #define MTD_1       mtd1
 #define MTD_2       mtd2
 #define MTD_NUMOF   3
+
+#define CONFIG_SDMMC_GENERIC_MTD_OFFSET     2   /**< mtd2 is used for SD Card */
 /** @} */
 
 /**

diff --git a/boards/same54-xpro/include/periph_conf.h b/boards/same54-xpro/include/periph_conf.h
@@ -369,6 +369,18 @@ static const adc_conf_chan_t adc_channels[] = {
  */
 #define SDHC_DEV            SDHC1       /**< The SDHC instance to use */
 #define SDHC_DEV_ISR        isr_sdhc1   /**< Interrupt service routing for SDHC1 */
+
+/** SDHC devices */
+static const sdhc_conf_t sdhc_config[] = {
+    {
+        .sdhc = SDHC1,
+        .cd = GPIO_PIN(PD, 20),
+        .wp = GPIO_UNDEF,
+    },
+};
+
+/** Number of configured SDHC devices */
+#define SDHC_CONFIG_NUMOF  1
 /** @} */
 
 /**

diff --git a/cpu/esp32/ld/esp32s2/sections.ld.in b/cpu/esp32/ld/esp32s2/sections.ld.in
@@ -590,9 +590,11 @@ SECTIONS
     _sheap = ABSOLUTE(.);
   } > dram0_0_seg
 
-  . = _heap_end;
+  . = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);
   _eheap = ABSOLUTE(.);
 
+  . = _heap_end;
+
 #ifdef MODULE_PERIPH_FLASHPAGE
   .flash_writable (NOLOAD) : ALIGN(65536)
   {

diff --git a/cpu/esp32/ld/esp32s3/sections.ld.in b/cpu/esp32/ld/esp32s3/sections.ld.in
@@ -213,6 +213,8 @@ SECTIONS
     *components/esp_hw_support/*/rtc_sleep.*(.literal .literal.* .text .text.*)
     *components/esp_hw_support/*/rtc_time.*(.literal .literal.* .text .text.*)
     *components/esp_hw_support/*/rtc_wdt.*(.literal .literal.* .text .text.*)
+    *components/esp_hw_support/*/spiram_psram.*(.literal .literal.* .text .text.*)
+    *components/esp_hw_support/*/opiram_psram.*(.literal .literal.* .text .text.*)
     *components/esp_ringbuf/*(.literal .literal.* .text .text.*)
     *components/esp_rom/esp_rom_spiflash.*(.literal .literal.* .text .text.*)
     *components/esp_system/esp_err.*(.literal .literal.* .text .text.*)
@@ -617,9 +619,11 @@ SECTIONS
     _sheap = ABSOLUTE(.);
   } > dram0_0_seg
 
-  . = _heap_end;
+  . = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);
   _eheap = ABSOLUTE(.);
 
+  . = _heap_end;
+
 #ifdef MODULE_PERIPH_FLASHPAGE
   .flash_writable (NOLOAD) : ALIGN(65536)
   {

diff --git a/cpu/sam0_common/Kconfig b/cpu/sam0_common/Kconfig
@@ -17,6 +17,10 @@ config CPU_COMMON_SAM0
     select HAS_PERIPH_I2C_RECONFIGURE
     select HAS_PERIPH_RTT_SET_COUNTER
     select HAS_PERIPH_RTT_OVERFLOW
+    select HAS_PERIPH_SDMMC_AUTO_CMD12
+    select HAS_PERIPH_SDMMC_HS
+    select HAS_PERIPH_SDMMC_MMC
+    select HAS_PERIPH_SDMMC_SDHC
     select HAS_PERIPH_SPI_RECONFIGURE
     select HAS_PERIPH_SPI_GPIO_MODE
     select HAS_PERIPH_TIMER_PERIODIC

diff --git a/cpu/sam0_common/Makefile.dep b/cpu/sam0_common/Makefile.dep
@@ -10,6 +10,10 @@ ifneq (,$(filter periph_spi,$(USEMODULE)))
   USEMODULE += periph_spi_gpio_mode
 endif
 
+ifneq (,$(filter periph_sdmmc,$(USEMODULE)))
+  USEMODULE += sdmmc_sdhc
+endif
+
 # include sam0 common periph drivers
 USEMODULE += sam0_common_periph
 

diff --git a/cpu/sam0_common/Makefile.features b/cpu/sam0_common/Makefile.features
@@ -15,6 +15,10 @@ FEATURES_PROVIDED += periph_gpio periph_gpio_irq
 FEATURES_PROVIDED += periph_i2c_reconfigure
 FEATURES_PROVIDED += periph_rtt_set_counter
 FEATURES_PROVIDED += periph_rtt_overflow
+FEATURES_PROVIDED += periph_sdmmc_auto_cmd12
+FEATURES_PROVIDED += periph_sdmmc_hs
+FEATURES_PROVIDED += periph_sdmmc_mmc
+FEATURES_PROVIDED += periph_sdmmc_sdhc
 FEATURES_PROVIDED += periph_spi_reconfigure
 FEATURES_PROVIDED += periph_spi_gpio_mode
 FEATURES_PROVIDED += periph_timer_periodic # implements timer_set_periodic()

diff --git a/cpu/sam0_common/include/periph_cpu_common.h b/cpu/sam0_common/include/periph_cpu_common.h
@@ -907,6 +907,25 @@ typedef struct {
 } sam0_common_usb_config_t;
 #endif /* USB_INST_NUM */
 
+/**
+ * @brief SDIO/SDMMC buffer alignment for SDHC because of DMA/FIFO buffer restrictions
+ */
+#define SDMMC_CPU_DMA_ALIGNMENT     4
+
+/**
+ * @brief SDIO/SDMMC buffer instantiation requirement for SDHC
+ */
+#define SDMMC_CPU_DMA_REQUIREMENTS  __attribute__((aligned(SDMMC_CPU_DMA_ALIGNMENT)))
+
+/**
+ * @brief SDHC peripheral configuration
+ */
+typedef struct {
+    void *sdhc; /**< SDHC peripheral */
+    gpio_t cd;  /**< Card Detect pin (must be GPIO_UNDEF if not connected) */
+    gpio_t wp;  /**< Write Protect pin (must be GPIO_UNDEF if not connected) */
+} sdhc_conf_t;
+
 /**
  * @name    WDT upper and lower bound times in ms
  * @{

diff --git a/cpu/sam0_common/include/sdhc.h b/cpu/sam0_common/include/sdhc.h
@@ -11,6 +11,9 @@
  * @ingroup     cpu_sam0_common
  * @brief       SD card interface functions for sam0 class devices
  *
+ * @warning     This driver is deprecated. Use the `sdmmc` driver module
+ *              instead. You can refer to the `same54-xpro´ board as an example
+ *              on how to use it.
  * @{
  *
  * @file

diff --git a/cpu/samd5x/include/periph_cpu.h b/cpu/samd5x/include/periph_cpu.h
@@ -54,6 +54,16 @@ extern "C" {
  * @{
  */
 #define PM_NUM_MODES            (4)     /**< Backup, Hibernate, Standby, Idle */
+
+/**
+ * @brief   Power modes
+ */
+enum {
+    SAM0_PM_BACKUP = 0,
+    SAM0_PM_HIBERNATE = 1,
+    SAM0_PM_STANDBY = 2,
+    SAM0_PM_IDLE = 3,
+};
 /** @} */
 
 /**