By setting max_trials, we limit the number of layouts
enumerated and scored when iterating through vf2_mapping().

This is necessary for scoring to complete in a reasonable
amount of time for circuits with many connected components
on larger (e.g. 400 qubit) devices.

These limits were chosen using a fake 400 qubit device,
using 200 connected components, where each component is
a single CX gate.

Because layout scoring scales linearly
with the number of qubits in the circuit, 250,000 (O3)
takes abount a minute, 25,000 (O2) takes about 6 seconds,
and 2,500 (O1) takes less than a second.