Update
- A bug of CoRAM signal insertion for nested instance/module is fixed (tests/multipage)
- Minor typos are fixed.
Test environment
Mac OSX 10.10.5
- python 2.7.9 + pyverilog 1.0.1
- python 3.4.2 + pyverilog 1.0.1
Ubuntu 14.04
- python 2.7.6 + pyverilog 1.0.1
- python 3.4.3 + pyverilog 1.0.1