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fix f1 build target
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dakejahl committed Oct 29, 2024
1 parent c4b7381 commit 4e672d9
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Showing 3 changed files with 15 additions and 42 deletions.
23 changes: 15 additions & 8 deletions platforms/nuttx/src/px4/stm/stm32_common/io_pins/io_timer.c
Original file line number Diff line number Diff line change
Expand Up @@ -73,8 +73,15 @@ static int io_timer_handler7(int irq, void *context, void *arg);

#if defined(HAVE_GTIM_CCXNP)
#define HW_GTIM_CCER_CC1NP GTIM_CCER_CC1NP
#define HW_GTIM_CCER_CC2NP GTIM_CCER_CC2NP
#define HW_GTIM_CCER_CC3NP GTIM_CCER_CC3NP
#define HW_GTIM_CCER_CC4NP GTIM_CCER_CC4NP

#else
# define HW_GTIM_CCER_CC1NP 0
# define HW_GTIM_CCER_CC2NP 0
# define HW_GTIM_CCER_CC3NP 0
# define HW_GTIM_CCER_CC4NP 0
#endif

#define arraySize(a) (sizeof((a))/sizeof(((a)[0])))
Expand Down Expand Up @@ -635,31 +642,31 @@ int io_timer_set_dshot_capture_mode(uint8_t timer, uint8_t timer_channel_index,
switch (timer_channel_index) {
case 0:
rEGR(timer) |= ATIM_EGR_UG | GTIM_EGR_CC1G;
rCCER(timer) &= ~(GTIM_CCER_CC1E | GTIM_CCER_CC1P | GTIM_CCER_CC1NP);
rCCER(timer) &= ~(GTIM_CCER_CC1E | GTIM_CCER_CC1P | HW_GTIM_CCER_CC1NP);
rCCMR1(timer) |= (GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC1S_SHIFT);
rCCER(timer) |= (GTIM_CCER_CC1E | GTIM_CCER_CC1P | GTIM_CCER_CC1NP);
rCCER(timer) |= (GTIM_CCER_CC1E | GTIM_CCER_CC1P | HW_GTIM_CCER_CC1NP);

break;

case 1:
rEGR(timer) |= ATIM_EGR_UG | GTIM_EGR_CC2G;
rCCER(timer) &= ~(GTIM_CCER_CC2E | GTIM_CCER_CC2P | GTIM_CCER_CC2NP);
rCCER(timer) &= ~(GTIM_CCER_CC2E | GTIM_CCER_CC2P | HW_GTIM_CCER_CC2NP);
rCCMR1(timer) |= (GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC2S_SHIFT);
rCCER(timer) |= (GTIM_CCER_CC2E | GTIM_CCER_CC2P | GTIM_CCER_CC2NP);
rCCER(timer) |= (GTIM_CCER_CC2E | GTIM_CCER_CC2P | HW_GTIM_CCER_CC2NP);
break;

case 2:
rEGR(timer) |= ATIM_EGR_UG | GTIM_EGR_CC3G;
rCCER(timer) &= ~(GTIM_CCER_CC3E | GTIM_CCER_CC3P | GTIM_CCER_CC3NP);
rCCER(timer) &= ~(GTIM_CCER_CC3E | GTIM_CCER_CC3P | HW_GTIM_CCER_CC3NP);
rCCMR2(timer) |= (GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR2_CC3S_SHIFT);
rCCER(timer) |= (GTIM_CCER_CC3E | GTIM_CCER_CC3P | GTIM_CCER_CC3NP);
rCCER(timer) |= (GTIM_CCER_CC3E | GTIM_CCER_CC3P | HW_GTIM_CCER_CC3NP);
break;

case 3:
rEGR(timer) |= ATIM_EGR_UG | GTIM_EGR_CC4G;
rCCER(timer) &= ~(GTIM_CCER_CC4E | GTIM_CCER_CC4P | GTIM_CCER_CC4NP);
rCCER(timer) &= ~(GTIM_CCER_CC4E | GTIM_CCER_CC4P | HW_GTIM_CCER_CC4NP);
rCCMR2(timer) |= (GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR2_CC4S_SHIFT);
rCCER(timer) |= (GTIM_CCER_CC4E | GTIM_CCER_CC4P | GTIM_CCER_CC4NP);
rCCER(timer) |= (GTIM_CCER_CC4E | GTIM_CCER_CC4P | HW_GTIM_CCER_CC4NP);
break;
}

Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -38,23 +38,6 @@
static inline constexpr void getTimerChannelDMAMap(Timer::Timer timer, const DMA &dma, uint32_t *dma_map_ch)
{
// Not supported
switch (timer) {
case Timer::Timer1:
case Timer::Timer2:
case Timer::Timer3:
case Timer::Timer4:
case Timer::Timer5:
case Timer::Timer6:
case Timer::Timer7:
case Timer::Timer8:
case Timer::Timer9:
case Timer::Timer10:
case Timer::Timer11:
case Timer::Timer12:
case Timer::Timer13:
case Timer::Timer14:
break;
}
}

static inline constexpr uint32_t getTimerUpdateDMAMap(Timer::Timer timer, const DMA &dma)
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -38,23 +38,6 @@
static inline constexpr void getTimerChannelDMAMap(Timer::Timer timer, const DMA &dma, uint32_t *dma_map_ch)
{
// Not supported
switch (timer) {
case Timer::Timer1:
case Timer::Timer2:
case Timer::Timer3:
case Timer::Timer4:
case Timer::Timer5:
case Timer::Timer6:
case Timer::Timer7:
case Timer::Timer8:
case Timer::Timer9:
case Timer::Timer10:
case Timer::Timer11:
case Timer::Timer12:
case Timer::Timer13:
case Timer::Timer14:
break;
}
}

static inline constexpr uint32_t getTimerUpdateDMAMap(Timer::Timer timer, const DMA &dma)
Expand Down

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