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Update README
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Matthew Naylor committed Sep 2, 2018
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8 changes: 4 additions & 4 deletions README.md
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Expand Up @@ -343,8 +343,8 @@ structure of each cache.
`LogDCachesPerDRAM` | 3 | Caches per DRAM
`DCacheLogWordsPerBeat` | 3 | Number of 32-bit words per beat
`DCacheLogBeatsPerLine` | 0 | Beats per cache line
`DCacheLogNumWays` | 3 | Cache lines in each associative set
`DCacheLogSetsPerThread` | 2 | Associative sets per thread
`DCacheLogNumWays` | 2 | Cache lines in each associative set
`DCacheLogSetsPerThread` | 3 | Associative sets per thread
`LogBeatsPerDRAM` | 26 | Size of DRAM

## 4. Tinsel Mailbox
Expand Down Expand Up @@ -805,8 +805,8 @@ ALMs, *58% of the DE5-Net*.
`LogDCachesPerDRAM` | 3 | Caches per DRAM
`DCacheLogWordsPerBeat` | 3 | Number of 32-bit words per beat
`DCacheLogBeatsPerLine` | 0 | Beats per cache line
`DCacheLogNumWays` | 3 | Cache lines in each associative set
`DCacheLogSetsPerThread` | 2 | Associative sets per thread
`DCacheLogNumWays` | 2 | Cache lines in each associative set
`DCacheLogSetsPerThread` | 3 | Associative sets per thread
`LogBeatsPerDRAM` | 26 | Size of DRAM
`SRAMAddrWidth` | 20 | Address width of each off-chip SRAM
`LogBytesPerSRAMBeat` | 3 | Data width of each off-chip SRAM
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