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@poemonsense
poemonsense committed Dec 18, 2023
1 parent d4b28b6 commit bc3aafa
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Showing 5 changed files with 5 additions and 5 deletions.
2 changes: 1 addition & 1 deletion DRAMsim3
Submodule DRAMsim3 updated 3 files
+67 −0 configs/XiangShan-nanhu.ini
+30 −30 configs/XiangShan.ini
+3 −3 src/cosimulation.h
2 changes: 1 addition & 1 deletion NEMU
Submodule NEMU updated 85 files
+12 −0 .github/workflows/ci.yml
+3 −0 .gitmodules
+14 −0 Kconfig
+3 −2 Makefile
+155 −0 configs/riscv64-rvv-diff-spike_defconfig
+1 −0 configs/riscv64-rvv-ref_defconfig
+132 −0 configs/riscv64-spm-ref-xs_defconfig
+147 −0 configs/riscv64-spm-xs_defconfig
+157 −0 configs/riscv64-xs-spmem-ref_defconfig
+131 −0 configs/riscv64-xs-spmem-so-ref_defconfig
+2 −1 include/checkpoint/path_manager.h
+0 −36 include/checkpoint/profiling.h
+2 −0 include/checkpoint/serializer.h
+2 −2 include/cpu/cpu.h
+2 −0 include/cpu/decode.h
+9 −0 include/cpu/difftest.h
+2 −0 include/debug.h
+16 −2 include/memory/paddr.h
+148 −0 include/memory/sparseram.h
+34 −0 include/profiling/profiling_control.h
+53 −1 include/rtl/fp.h
+1 −0 include/rtl/rtl.h
+1 −0 include/utils.h
+48 −0 modify_pointdir_structure.py
+52 −0 onesimpoint.py
+1 −1 ready-to-run
+1 −1 resource/gcpt_restore/Makefile
+18 −0 resource/gcpt_restore/src/csr.h
+7 −2 resource/gcpt_restore/src/restore.S
+107 −0 resource/simpoint/do_simpoint_clustering.py
+1 −0 resource/simpoint/simpoint_repo
+5 −5 scripts/build.mk
+8 −0 scripts/manual-take.sh
+1 −1 scripts/restore.sh
+34 −20 src/checkpoint/path_manager.cpp
+0 −29 src/checkpoint/profiling.c
+56 −25 src/checkpoint/serializer.cpp
+19 −13 src/checkpoint/simpoint.cpp
+262 −166 src/cpu/cpu-exec.c
+34 −0 src/cpu/difftest/ref.c
+1 −1 src/device/device.c
+8 −0 src/device/disk.c
+1 −1 src/device/flash.c
+263 −0 src/engine/interpreter/fp.c
+2 −0 src/engine/interpreter/hostcall.c
+3 −3 src/engine/interpreter/rtl-basic.h
+522 −0 src/engine/interpreter/softfloat-fp.h
+10 −0 src/isa/riscv64/Kconfig
+23 −51 src/isa/riscv64/difftest/dut.c
+13 −10 src/isa/riscv64/difftest/ref.c
+18 −4 src/isa/riscv64/include/isa-all-instr.h
+26 −19 src/isa/riscv64/include/isa-def.h
+11 −2 src/isa/riscv64/init.c
+7 −0 src/isa/riscv64/instr/fp.c
+4 −4 src/isa/riscv64/instr/priv/decode.h
+6 −0 src/isa/riscv64/instr/priv/system.c
+8 −2 src/isa/riscv64/instr/rva/amo.c
+12 −10 src/isa/riscv64/instr/rvf/decode.h
+146 −11 src/isa/riscv64/instr/rvv/decode.h
+12 −5 src/isa/riscv64/instr/rvv/vcfg.h
+27 −0 src/isa/riscv64/instr/rvv/vcommon.c
+15 −0 src/isa/riscv64/instr/rvv/vcommon.h
+424 −35 src/isa/riscv64/instr/rvv/vcompute.h
+600 −49 src/isa/riscv64/instr/rvv/vcompute_impl.c
+38 −3 src/isa/riscv64/instr/rvv/vcompute_impl.h
+24 −0 src/isa/riscv64/instr/rvv/vldst.h
+88 −35 src/isa/riscv64/instr/rvv/vldst_impl.c
+1 −0 src/isa/riscv64/instr/rvv/vldst_impl.h
+36 −0 src/isa/riscv64/instr/rvv/vreg.h
+73 −8 src/isa/riscv64/instr/rvv/vreg_impl.c
+9 −9 src/isa/riscv64/instr/special.h
+12 −1 src/isa/riscv64/local-include/csr.h
+2 −0 src/isa/riscv64/local-include/vreg.h
+6 −0 src/isa/riscv64/system/mmu.c
+9 −3 src/isa/riscv64/system/priv.c
+4 −0 src/memory/Kconfig
+18 −0 src/memory/host-tlb.c
+42 −15 src/memory/paddr.c
+814 −0 src/memory/sparseram.cpp
+7 −1 src/memory/vaddr.c
+24 −3 src/monitor/image_loader.c
+102 −17 src/monitor/monitor.c
+28 −0 src/profiling/profiling_control.c
+3 −3 src/utils/dynamic-config.c
+4 −0 src/utils/state.c
2 changes: 1 addition & 1 deletion NutShell
Submodule NutShell updated 64 files
+34 −3 .github/workflows/main.yml
+1 −0 .gitignore
+2 −1 .mill-version
+46 −6 Makefile
+27 −12 build.sc
+1 −1 difftest
+81 −0 generator/chisel/src/main/scala/TopMain.scala
+13 −13 generator/chisel3/src/main/scala/TopMain.scala
+ − ready-to-run/riscv64-nemu-interpreter-so
+52 −0 scripts/extract_files.sh
+5 −5 src/main/scala/bus/axi4/AXI4.scala
+23 −23 src/main/scala/bus/simplebus/Crossbar.scala
+13 −13 src/main/scala/bus/simplebus/DistributedMem.scala
+24 −24 src/main/scala/bus/simplebus/SimpleBus.scala
+22 −22 src/main/scala/bus/simplebus/ToAXI4.scala
+15 −13 src/main/scala/device/AXI4CLINT.scala
+16 −15 src/main/scala/device/AXI4DMA.scala
+11 −11 src/main/scala/device/AXI4DummySD.scala
+9 −9 src/main/scala/device/AXI4Flash.scala
+12 −10 src/main/scala/device/AXI4PLIC.scala
+21 −33 src/main/scala/device/AXI4RAM.scala
+24 −24 src/main/scala/device/AXI4Slave.scala
+11 −11 src/main/scala/device/AXI4UART.scala
+19 −13 src/main/scala/device/AXI4VGA.scala
+10 −10 src/main/scala/nutcore/Decode.scala
+14 −13 src/main/scala/nutcore/NutCore.scala
+25 −25 src/main/scala/nutcore/backend/fu/ALU.scala
+67 −50 src/main/scala/nutcore/backend/fu/CSR.scala
+72 −72 src/main/scala/nutcore/backend/fu/LSU.scala
+12 −12 src/main/scala/nutcore/backend/fu/MDU.scala
+10 −10 src/main/scala/nutcore/backend/fu/MOU.scala
+63 −63 src/main/scala/nutcore/backend/fu/UnpipelinedLSU.scala
+82 −84 src/main/scala/nutcore/backend/ooo/Backend.scala
+49 −52 src/main/scala/nutcore/backend/ooo/ROB.scala
+57 −57 src/main/scala/nutcore/backend/ooo/RS.scala
+26 −27 src/main/scala/nutcore/backend/seq/EXU.scala
+20 −21 src/main/scala/nutcore/backend/seq/ISU.scala
+18 −45 src/main/scala/nutcore/backend/seq/WBU.scala
+22 −19 src/main/scala/nutcore/frontend/BPU.scala
+10 −12 src/main/scala/nutcore/frontend/Frontend.scala
+17 −17 src/main/scala/nutcore/frontend/IBF.scala
+17 −27 src/main/scala/nutcore/frontend/IDU.scala
+46 −46 src/main/scala/nutcore/frontend/IFU.scala
+27 −27 src/main/scala/nutcore/frontend/NaiveIBF.scala
+1 −1 src/main/scala/nutcore/isa/Priviledged.scala
+1 −1 src/main/scala/nutcore/isa/RVI.scala
+3 −3 src/main/scala/nutcore/isa/RVM.scala
+86 −88 src/main/scala/nutcore/mem/Cache.scala
+57 −53 src/main/scala/nutcore/mem/EmbeddedTLB.scala
+47 −47 src/main/scala/nutcore/mem/TLB.scala
+16 −16 src/main/scala/nutcore/utils/WritebackDelayer.scala
+9 −9 src/main/scala/sim/MeipGen.scala
+15 −19 src/main/scala/sim/NutShellSim.scala
+7 −7 src/main/scala/sim/SimMMIO.scala
+15 −15 src/main/scala/system/Coherence.scala
+4 −4 src/main/scala/system/NutShell.scala
+14 −14 src/main/scala/system/Prefetcher.scala
+13 −11 src/main/scala/utils/BitUtils.scala
+3 −3 src/main/scala/utils/FlushableQueue.scala
+7 −6 src/main/scala/utils/LatencyPipe.scala
+13 −13 src/main/scala/utils/PipelineVector.scala
+9 −9 src/main/scala/utils/SRAMTemplate.scala
+16 −16 src/test/scala/cache/CacheTest.scala
+0 −41 src/test/vsrc/ram.v
2 changes: 1 addition & 1 deletion XiangShan
Submodule XiangShan updated 221 files
2 changes: 1 addition & 1 deletion nexus-am
Submodule nexus-am updated 6 files
+4 −0 apps/coremark/Makefile
+2 −0 apps/coremark/include/core_portme.h
+0 −0 tests/oraclebptest/Makefile
+0 −0 tests/oraclebptest/README.md
+0 −0 tests/oraclebptest/include/test.h
+0 −0 tests/oraclebptest/src/main.c

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