Add GC4023 for Gk7205v200

general/package/goke-osdrv-gk7205v200/files/sensor/config/gc4023_i2c_4M.ini

@@ -0,0 +1,66 @@
+[sensor]
+Sensor_type=stSnsGc4023Obj
+Mode=WDR_MODE_NONE
+DllFile=libsns_gc4023.so
+
+[mode]
+input_mode=INPUT_MODE_MIPI
+raw_bitness=10
+
+[mipi]
+lane_id = 0|2|-1|-1|-1|-1|-1|-1|          ;lane_id: -1 - disable
+
+[isp_image]
+Isp_FrameRate=25
+Isp_Bayer=BAYER_RGGB
+
+[vi_dev]
+Input_mod=VI_MODE_MIPI
+Work_mod     = VI_WORK_MODE_1Multiplex
+Mask_num     = 2
+Mask_0       = 0xFFC00000
+Mask_1       = 0x0
+Scan_mode    = VI_SCAN_PROGRESSIVE
+Data_seq     = VI_DATA_SEQ_YUYV
+Vsync   =1      ; vertical synchronization signal
+                ;VI_VSYNC_PULSE,
+VsyncNeg=1      ;Polarity of the vertical synchronization signal
+                ;VI_VSYNC_NEG_HIGH = 0,
+                ;VI_VSYNC_NEG_LOW /*if VIU_VSYNC_E
+Hsync  =0       ;Attribute of the horizontal synchronization signal
+                ;VI_HSYNC_VALID_SINGNAL = 0,
+                ;VI_HSYNC_PULSE,
+HsyncNeg =0     ;Polarity of the horizontal synchronization signal
+                ;VI_HSYNC_NEG_HIGH = 0,
+                ;VI_HSYNC_NEG_LOW
+VsyncValid =1   ;Attribute of the valid vertical synchronization signal
+                ;VI_VSYNC_NORM_PULSE = 0,
+                ;VI_VSYNC_VALID_SINGAL,
+VsyncValidNeg =0;Polarity of the valid vertical synchronization signal
+                ;VI_VSYNC_VALID_NEG_HIGH = 0,
+                ;VI_VSYNC_VALID_NEG_LOW
+Timingblank_HsyncHfb =0     ;Horizontal front blanking width
+Timingblank_HsyncAct =2560  ;Horizontal effetive width
+Timingblank_HsyncHbb =0     ;Horizontal back blanking width
+Timingblank_VsyncVfb =0     ;Vertical front blanking height
+Timingblank_VsyncVact =1440  ;Vertical effetive width
+Timingblank_VsyncVbb=0      ;Vertical back blanking height
+Timingblank_VsyncVbfb =0    ;Even-field vertical front blanking height(interlace, invalid progressive)
+Timingblank_VsyncVbact=0    ;Even-field vertical effetive width(interlace, invalid progressive)
+Timingblank_VsyncVbbb =0    ;Even-field vertical back blanking height(interlace, invalid progressive)
+InputDataType=1 ;VI_DATA_TYPE_YUV = 0,VI_DATA_TYPE_RGB = 1,
+DataRev      =FALSE ;Data reverse. FALSE = 0; TRUE = 1
+DevRect_w=2560
+DevRect_h=1440
+DevRect_x=0
+DevRect_y=0
+
+Combine_mode =0 ;Y/C composite or separation mode
+                ;VI_COMBINE_COMPOSITE = 0 /*Composite mode */
+                ;VI_COMBINE_SEPARATE,     /*Separate mode */
+Comp_mode    =0 ;Component mode (single-component or dual-component)
+                ;VI_COMP_MODE_SINGLE = 0, /*single component mode */
+                ;VI_COMP_MODE_DOUBLE = 1, /*double component mode */
+Clock_edge   =1 ;Clock edge mode (sampling on the rising or falling edge)
+                ;VI_CLK_EDGE_SINGLE_UP=0, /*rising edge */
+                ;VI_CLK_EDGE_SINGLE_DOWN, /*falling edge */