hdl: Added ATSC TX FPGA implementation

This revision introduces an FPGA-based ATSC transmitter to offload the
pilot insertion, filtering, and shift to baseband.

This design expects that 4-bit ATSC symbols are written to the device in
little-endian 32-bit words, as shown below.

        |<-------                               32 Bit Word                                     ------->|
Bit     |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
Symbol  [ X|   7    ][X|  6     ][X|   5    ][X|    4   ][X|   3   ][X|   2     ][X|    1   ][X|    0   ]

The FPGA transmits Symbol 0 first, and Symbol 7 last. The three
least-significant bits in each symbol's nibble contain values 0 to 7,
mapping to values of -7 to 7, with the most-significant bit left unused.

This FPGA image may be built by specifying the "atsc_tx" image to the
build_bladerf.sh script. The resulting output files will be
atsc_txx40.rbf and atsc_txx115.rbf for the x40 and the x115,
respectively.

Transmitting a pre-made stream on channel 14-1 can be achieved with the
following commands in the bladeRF-cli:

    set frequency 473000000
    set samplerate 32286713 2867 10000

    set txvga1 -4
    set txvga2 20

    tx config file=<path to file> repeat=0 delay=0
    tx start

hdl/fpga/ip/nuand/nuand.do

@@ -1,6 +1,9 @@
 proc compile_nuand { root } {
     vlib nuand
 
+    vcom -work nuand -2008 [file join $root ../altera/tx_fifo/tx_fifo.vhd]
+
+
     vcom -work nuand -2008 [file join $root ./synthesis/constellation_mapper.vhd]
     vcom -work nuand -2008 [file join $root ./synthesis/sync_fifo.vhd]
     vcom -work nuand -2008 [file join $root ./synthesis/uart.vhd]
@@ -18,7 +21,16 @@ proc compile_nuand { root } {
     vcom -work nuand -2008 [file join $root ./synthesis/handshake.vhd]
     vcom -work nuand -2008 [file join $root ./synthesis/tb/handshake_tb.vhd]
 
+    vcom -work nuand -2008 [file join $root ./synthesis/signal_processing_p.vhd]
+
+    vcom -work nuand -2008 [file join $root ./synthesis/bit_stripper.vhd]
+    vcom -work nuand -2008 [file join $root ./synthesis/fir_filter.vhd]
+    vcom -work nuand -2008 [file join $root ./synthesis/atsc_tx.vhd]
     vcom -work nuand -2008 [file join $root ./simulation/util.vhd]
+    vcom -work nuand -2008 [file join $root ./synthesis/tb/fir_filter_tb.vhd]
+
+    vcom -work nuand -2008 [file join $root ./synthesis/tb/atsc_tx_tb.vhd]
+
     vcom -work nuand -2008 [file join $root ./simulation/fx3_model.vhd]
     vcom -work nuand -2008 [file join $root ./simulation/lms6002d_model.vhd]
 }

hdl/fpga/ip/nuand/simulation/util.vhd

@@ -1,6 +1,10 @@
 library ieee ;
     use ieee.std_logic_1164.all ;
 
+library std;
+    use std.textio.all;
+
+
 -- Utility package
 package util is
 
@@ -19,3 +23,169 @@ package body util is
 
 end package body ;
 
+library ieee ;
+    use ieee.std_logic_1164.all ;
+    use ieee.numeric_std.all;
+library std;
+    use std.textio.all;
+
+
+entity data_saver is
+    generic(
+        FILENAME : string := "file.dat";
+        DATA_WIDTH : natural := 16
+    );
+    port(
+        reset   : in std_logic;
+        clock   : in std_logic;
+        data    : std_logic_vector(DATA_WIDTH-1 downto 0);
+        data_valid : std_logic
+    );
+end entity;
+
+
+architecture arch of data_saver is
+begin
+
+    handler : process
+        FILE fp : text;
+        variable line_data : line;
+    begin
+        --
+        wait until falling_edge(reset);
+
+            file_open(fp, FILENAME, WRITE_MODE);
+
+            while (reset = '0') loop
+                wait until rising_edge(data_valid);
+                    write(line_data, data);
+                    writeline(fp,line_data);
+            end loop;
+            file_close(fp);
+    end process;
+end architecture;
+
+
+library ieee ;
+    use ieee.std_logic_1164.all ;
+    use ieee.numeric_std.all;
+library std;
+    use std.textio.all;
+
+
+entity signed_saver is
+    generic(
+        FILENAME : string := "file.dat";
+        DATA_WIDTH : natural := 16
+    );
+    port(
+        reset   : in std_logic;
+        clock   : in std_logic;
+        data    : signed(DATA_WIDTH-1 downto 0);
+        data_valid : std_logic
+    );
+end entity;
+
+
+architecture arch of signed_saver is
+begin
+
+    handler : process
+        FILE fp : text;
+        variable line_data : line;
+    begin
+        --
+        wait until falling_edge(reset);
+
+            file_open(fp, FILENAME, WRITE_MODE);
+
+            while (reset = '0') loop
+                wait until rising_edge(clock);
+
+                if data_valid = '1' then
+                    write(line_data, (to_integer(data)));
+                    writeline(fp,line_data);
+                end if;
+            end loop;
+            file_close(fp);
+    end process;
+end architecture;
+
+
+
+library ieee ;
+    use ieee.std_logic_1164.all ;
+    use ieee.numeric_std.all;
+library std;
+    use std.textio.all;
+
+
+entity data_reader is
+    generic(
+        FILENAME : string := "file.dat";
+        DATA_WIDTH : natural := 16
+    );
+    port(
+        reset   : in std_logic;
+        clock   : in std_logic;
+        data_request : in std_logic;
+        data    : out std_logic_vector(DATA_WIDTH-1 downto 0);
+        data_valid : out std_logic
+    );
+end entity;
+
+
+architecture arch of data_reader is
+
+    type character_array_t is array (natural range <>) of character;
+begin
+
+    handler : process
+        variable line_data : line;
+        variable tmp : integer;
+        variable c : character;--_array_t(0 to 3);
+
+        type bin_t is file of character ;
+        file fp : bin_t ;
+        variable fs : file_open_status ;
+    begin
+        --
+        data <= (others => '0');
+        data_valid <= '0';
+        wait until falling_edge(reset);
+
+            file_open(fs, fp, FILENAME, READ_MODE);
+
+            if( fs /= OPEN_OK ) then
+                report "File open issues" severity failure ;
+             end if ;
+
+            --readline(fp,line_data);
+            while (reset = '0') loop
+
+                wait until rising_edge(clock);
+                data_valid <= '0';
+
+                if data_request = '1' then
+                    read(fp, c);
+                    tmp := integer(natural(character'pos(c)));
+                    data(7 downto 0) <= std_logic_vector(to_unsigned(tmp,8));
+                    read(fp, c);
+                    tmp := integer(natural(character'pos(c)));
+                    data(15 downto 8) <= std_logic_vector(to_unsigned(tmp,8));
+                    read(fp, c);
+                    tmp := integer(natural(character'pos(c)));
+                    data(23 downto 16) <= std_logic_vector(to_unsigned(tmp,8));
+                    read(fp, c);
+                    tmp := integer(natural(character'pos(c)));
+                    data(31 downto 24) <= std_logic_vector(to_unsigned(tmp,8));
+
+                    data_valid <= '1';
+                    wait until rising_edge(clock);
+                    data_valid <= '0';
+                end if;
+
+            end loop;
+            file_close(fp);
+    end process;
+end architecture;