[VTA][Chisel] add scalafmt and format existing scala codebase (apache…

…#3880)

* [VTA][Chisel] add scalafmt and format existing scala codebase

* change column width to 100

* add scalafmt conf file as a valid file type

* add asf header to scalafmt conf file and rerun formatter

tests/lint/check_file_type.py

@@ -87,6 +87,7 @@
     ".clang-format",
     ".gitmodules",
     "CODEOWNERS",
+    ".scalafmt.conf",
    }
 
 # List of specific files allowed in relpath to <proj_root>

vta/apps/tsim_example/hardware/chisel/.scalafmt.conf

@@ -0,0 +1,21 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+maxColumn = 100
+rewrite.rules = [SortModifiers, SortImports]

vta/apps/tsim_example/hardware/chisel/Makefile

@@ -91,7 +91,10 @@ else
   lib_path = $(build_dir)/$(LIBNAME).so
 endif
 
-default: lib
+default: lint lib
+
+lint:
+	sbt scalafmt
 
 lib: $(lib_path)
 $(lib_path): $(verilator_build_dir)/V$(TOP).cpp

vta/apps/tsim_example/hardware/chisel/project/plugins.sbt

@@ -18,3 +18,4 @@
  */
 
 logLevel := Level.Warn
+addSbtPlugin("com.geirsson" % "sbt-scalafmt" % "1.5.1")

vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/Accel.scala

@@ -41,7 +41,7 @@ case class AccelConfig() {
   val nVals = 2
   val nPtrs = 2
   val regBits = 32
-  val ptrBits = 2*regBits
+  val ptrBits = 2 * regBits
 }
 
 class Accel extends Module {

vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/Compute.scala

@@ -54,27 +54,27 @@ class Compute(implicit config: AccelConfig) extends Module {
   val raddr = Reg(UInt(config.ptrBits.W))
   val waddr = Reg(UInt(config.ptrBits.W))
 
-  switch (state) {
-    is (sIdle) {
-      when (io.launch) {
+  switch(state) {
+    is(sIdle) {
+      when(io.launch) {
         state := sReadReq
       }
     }
-    is (sReadReq) {
+    is(sReadReq) {
       state := sReadData
     }
-    is (sReadData) {
-      when (io.mem.rd.valid) {
+    is(sReadData) {
+      when(io.mem.rd.valid) {
         state := sWriteReq
       }
     }
-    is (sWriteReq) {
+    is(sWriteReq) {
       state := sWriteData
     }
-    is (sWriteData) {
-      when (cnt === (length - 1.U)) {
+    is(sWriteData) {
+      when(cnt === (length - 1.U)) {
         state := sIdle
-      } .otherwise {
+      }.otherwise {
         state := sReadReq
       }
     }
@@ -83,20 +83,20 @@ class Compute(implicit config: AccelConfig) extends Module {
   val last = state === sWriteData && cnt === (length - 1.U)
 
   // cycle counter
-  when (state === sIdle) {
+  when(state === sIdle) {
     cycles := 0.U
-  } .otherwise {
+  }.otherwise {
     cycles := cycles + 1.U
   }
 
   io.ecnt(0).valid := last
   io.ecnt(0).bits := cycles
 
   // calculate next address
-  when (state === sIdle) {
+  when(state === sIdle) {
     raddr := io.ptrs(0)
     waddr := io.ptrs(1)
-  } .elsewhen (state === sWriteData) { // increment by 8-bytes
+  }.elsewhen(state === sWriteData) { // increment by 8-bytes
     raddr := raddr + 8.U
     waddr := waddr + 8.U
   }
@@ -108,7 +108,7 @@ class Compute(implicit config: AccelConfig) extends Module {
   io.mem.req.addr := Mux(state === sReadReq, raddr, waddr)
 
   // read
-  when (state === sReadData && io.mem.rd.valid) {
+  when(state === sReadData && io.mem.rd.valid) {
     reg := io.mem.rd.bits + const
   }
   io.mem.rd.ready := state === sReadData
@@ -118,9 +118,9 @@ class Compute(implicit config: AccelConfig) extends Module {
   io.mem.wr.bits := reg
 
   // count read/write
-  when (state === sIdle) {
+  when(state === sIdle) {
     cnt := 0.U
-  } .elsewhen (state === sWriteData) {
+  }.elsewhen(state === sWriteData) {
     cnt := cnt + 1.U
   }
 

vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/RegFile.scala

@@ -59,52 +59,54 @@ class RegFile(implicit config: AccelConfig) extends Module {
   val sIdle :: sRead :: Nil = Enum(2)
   val state = RegInit(sIdle)
 
-  switch (state) {
-    is (sIdle) {
-      when (io.host.req.valid && !io.host.req.opcode) {
+  switch(state) {
+    is(sIdle) {
+      when(io.host.req.valid && !io.host.req.opcode) {
         state := sRead
       }
     }
-    is (sRead) {
+    is(sRead) {
       state := sIdle
     }
   }
 
   io.host.req.deq := state === sIdle & io.host.req.valid
 
-  val nTotal = config.nCtrl + config.nECnt + config.nVals + (2*config.nPtrs)
-  val reg = Seq.fill(nTotal)(RegInit(0.U.asTypeOf(chiselTypeOf(io.host.req.value))))
+  val nTotal = config.nCtrl + config.nECnt + config.nVals + (2 * config.nPtrs)
+  val reg =
+    Seq.fill(nTotal)(RegInit(0.U.asTypeOf(chiselTypeOf(io.host.req.value))))
   val addr = Seq.tabulate(nTotal)(_ * 4)
-  val reg_map = (addr zip reg)  map { case (a, r) => a.U -> r }
+  val reg_map = (addr zip reg) map { case (a, r) => a.U -> r }
   val eo = config.nCtrl
   val vo = eo + config.nECnt
   val po = vo + config.nVals
 
-  when (io.finish) {
+  when(io.finish) {
     reg(0) := "b_10".U
-  } .elsewhen (state === sIdle && io.host.req.valid &&
-        io.host.req.opcode && addr(0).U === io.host.req.addr) {
+  }.elsewhen(state === sIdle && io.host.req.valid &&
+    io.host.req.opcode && addr(0).U === io.host.req.addr) {
     reg(0) := io.host.req.value
   }
 
   for (i <- 0 until config.nECnt) {
-    when (io.ecnt(i).valid) {
+    when(io.ecnt(i).valid) {
       reg(eo + i) := io.ecnt(i).bits
-    } .elsewhen (state === sIdle && io.host.req.valid &&
-          io.host.req.opcode && addr(eo + i).U === io.host.req.addr) {
+    }.elsewhen(state === sIdle && io.host.req.valid &&
+      io.host.req.opcode && addr(eo + i).U === io.host.req.addr) {
       reg(eo + i) := io.host.req.value
     }
   }
 
-  for (i <- 0 until (config.nVals + (2*config.nPtrs))) {
-    when (state === sIdle && io.host.req.valid &&
-          io.host.req.opcode && addr(vo + i).U === io.host.req.addr) {
+  for (i <- 0 until (config.nVals + (2 * config.nPtrs))) {
+    when(
+      state === sIdle && io.host.req.valid &&
+        io.host.req.opcode && addr(vo + i).U === io.host.req.addr) {
       reg(vo + i) := io.host.req.value
     }
   }
 
   val rdata = RegInit(0.U.asTypeOf(chiselTypeOf(io.host.req.value)))
-  when (state === sIdle && io.host.req.valid && !io.host.req.opcode) {
+  when(state === sIdle && io.host.req.valid && !io.host.req.opcode) {
     rdata := MuxLookup(io.host.req.addr, 0.U, reg_map)
   }
 
@@ -118,6 +120,6 @@ class RegFile(implicit config: AccelConfig) extends Module {
   }
 
   for (i <- 0 until config.nPtrs) {
-    io.ptrs(i) := Cat(reg(po + 2*i + 1), reg(po + 2*i))
+    io.ptrs(i) := Cat(reg(po + (2 * i) + 1), reg(po + (2 * i)))
   }
 }

vta/hardware/chisel/.scalafmt.conf

@@ -0,0 +1,21 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+maxColumn = 100
+rewrite.rules = [SortModifiers, SortImports]

vta/hardware/chisel/Makefile

@@ -102,7 +102,10 @@ else
   lib_path = $(vta_dir)/$(BUILD_NAME)/$(VTA_LIBNAME).so
 endif
 
-default: lib
+default: lint lib
+
+lint:
+	sbt scalafmt
 
 lib: $(lib_path)
 

vta/hardware/chisel/project/plugins.sbt

@@ -18,3 +18,4 @@
  */
 
 logLevel := Level.Warn
+addSbtPlugin("com.geirsson" % "sbt-scalafmt" % "1.5.1")