ARM: Issue a warning when the MRRC and MRRC2 instructions are used wi…

…th the same destination registers. * config/tc-arm.c (do_co_reg2c): Added constraint. * testsuite/gas/arm/dest-unpredictable.s: New. * testsuite/gas/arm/dest-unpredictable.l: New. * testsuite/gas/arm/dest-unpredictable.d: New.
Manishearth · Aug 19, 2016 · 873f10f · 873f10f
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diff --git a/gas/ChangeLog b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2016-08-19  Tamar Christina  <[email protected]>
+
+	* config/tc-arm.c (do_co_reg2c): Added constraint.
+	* testsuite/gas/arm/dest-unpredictable.s: New.
+	* testsuite/gas/arm/dest-unpredictable.l: New.
+	* testsuite/gas/arm/dest-unpredictable.d: New.
+
 2016-08-19  Nick Clifton  <[email protected]>
 
 	* testsuite/gas/i386/ilp32/x86-64-unwind.d: Adjust expected

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
@@ -8691,6 +8691,14 @@ do_co_reg2c (void)
       constraint (Rn == REG_PC, BAD_PC);
     }
 
+  /* Only check the MRRC{2} variants.  */
+  if ((inst.instruction & 0x0FF00000) == 0x0C500000)
+    {
+       /* If Rd == Rn, error that the operation is
+	  unpredictable (example MRRC p3,#1,r1,r1,c4).  */
+       constraint (Rd == Rn, BAD_OVERLAP);
+    }
+
   inst.instruction |= inst.operands[0].reg << 8;
   inst.instruction |= inst.operands[1].imm << 4;
   inst.instruction |= Rd << 12;

diff --git a/gas/testsuite/gas/arm/dest-unpredictable.d b/gas/testsuite/gas/arm/dest-unpredictable.d
@@ -0,0 +1,2 @@
+# name: Unpredictable MRRC and MRRC2 instructions. - ARM
+# error-output: dest-unpredictable.l
diff --git a/gas/testsuite/gas/arm/dest-unpredictable.l b/gas/testsuite/gas/arm/dest-unpredictable.l
@@ -0,0 +1,5 @@
+[^:]*: Assembler messages:
+[^:]*:6: Error: registers may not be the same -- `mrrc p0,#1,r1,r1,c4'
+[^:]*:7: Error: registers may not be the same -- `mrrc2 p0,#1,r1,r1,c4'
+[^:]*:20: Error: registers may not be the same -- `mrrc p0,#1,r1,r1,c4'
+[^:]*:21: Error: registers may not be the same -- `mrrc2 p0,#1,r1,r1,c4'
diff --git a/gas/testsuite/gas/arm/dest-unpredictable.s b/gas/testsuite/gas/arm/dest-unpredictable.s
@@ -0,0 +1,29 @@
+.syntax unified
+
+.arm
+
+@ warnings
+mrrc  p0,#1,r1,r1,c4		@ unpredictable
+mrrc2 p0,#1,r1,r1,c4		@ ditto
+
+@ normal
+mrrc  p0,#1,r1,r2,c4		@ predictable
+mrrc2 p0,#1,r1,r2,c4		@ ditto
+mcrr  p0,#1,r1,r2,c4		@ ditto
+mcrr2 p0,#1,r1,r2,c4		@ ditto
+mcrr  p0,#1,r1,r1,c4		@ ditto
+mcrr2 p0,#1,r1,r1,c4		@ ditto
+
+.thumb
+
+@ warnings
+mrrc  p0,#1,r1,r1,c4		@ unpredictable
+mrrc2 p0,#1,r1,r1,c4		@ ditto
+
+@ normal
+mrrc  p0,#1,r1,r2,c4		@ predictable
+mrrc2 p0,#1,r1,r2,c4		@ ditto
+mcrr  p0,#1,r1,r2,c4		@ ditto
+mcrr2 p0,#1,r1,r2,c4		@ ditto
+mcrr  p0,#1,r1,r1,c4		@ ditto
+mcrr2 p0,#1,r1,r1,c4		@ ditto
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1,2 @@
		# name: Unpredictable MRRC and MRRC2 instructions. - ARM
		# error-output: dest-unpredictable.l