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Make: generate dependency files #85
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TestingBEFORE
AFTER
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Makefile
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@@ -89,9 +89,14 @@ $(TARGET): $(OBJS) | |||
@echo "AS " $@ | |||
@ $(CC) -c -o $@ $(AFLAGS) $< | |||
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DEPFLAGS := -MMD |
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The flag is already part of COMMON_FLAGS.
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Fun. Then we only need the rule to actually include those dep files.
Makefile
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%.o: %.c | ||
@echo "CC " $@ | ||
@ $(CC) -c -o $@ $(CFLAGS) $< | ||
@$(CC) -c -o $@ $(CFLAGS) $(DEPFLAGS) $< |
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Not needed, -MMD should be there
While we are at it, can we also store all *.d in a dedicated dir like: .deps ? Is the dependency for a linker script also covered? |
Let's leave that for later.
I pulled the PREP_LINK_SCRIPT generation into a separate rule. |
Makefile
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%.o: %.S | ||
@echo "AS " $@ | ||
@ $(CC) -c -o $@ $(AFLAGS) $< | ||
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%.o: %.c | ||
@echo "CC " $@ | ||
@ $(CC) -c -o $@ $(CFLAGS) $< | ||
@$(CC) -c -o $@ $(CFLAGS) $< |
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nit: change not needed
Generate dependency files for our C files so that we actually rebuild them when local header files are modified. Signed-off-by: Bjoern Doebel <[email protected]>
Signed-off-by: Bjoern Doebel <[email protected]>
Generate dependency files for our C files so that we actually rebuild them when
local header files are modified.
Signed-off-by: Bjoern Doebel [email protected]
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