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This change introduces support for MTRRs. PAT support has already been added.
This is an older way to control access and cacheability of physical memory regions.
Issue KernelTestFramework#180
Signed-off-by: Daniele Ahmed <[email protected]>
This change introduces support for MTRRs. PAT support has already been added.
This is an older way to control access and cacheability of physical memory regions.
Issue KernelTestFramework#180
Signed-off-by: Daniele Ahmed <[email protected]>
This change introduces support for MTRRs. PAT support has already been added.
This is an older way to control access and cacheability of physical memory regions.
Issue #180
Signed-off-by: Daniele Ahmed <[email protected]>
Is your feature request related to a problem? Please describe.
This feature request is to support page attribute tables and memory type range registers.
Useful for #179 too
Describe the solution you'd like
Have an API to configure the registers to control how memory is cached.
Describe alternatives you've considered
Keep using MSR's wherever possible.
Additional context
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