2019 01 19

Persistence and some Reworks

There is little use in extracting the netlist if you cannot do something with it. Plus, as extraction takes a while you want to save the results. This is what persistence is for.

Essentially the scheme is

iter = ... # the RecursiveShapeIterator for your layout hierarchy
l2n = RBA::LayoutToNetlist::new(iter)

... extract devices, nets ...

l2n.write("myfile.l2n")

# to read the data back
l2n = RBA::LayoutToNetlist::new
l2n.read("myfile.l2n")

To cover this requirement, I had to introduce two new features:

• Device abstracts: A device abstract describes a device in terms of shapes. Device abstracts sit between the device class (a generic type of device) and the device itself (the actual instance). Device abstracts carry the shapes of the device terminals and correspond to a layout cell.

• Named layers: Layers derived from LayoutToNetlist have to be named so they can be put into the file. Named layers carry an extended meaning: only named layers are kept within the LayoutToNetlist object. All other layers will be discarded when no longer used. This is in particular useful for computed layers. Only named layers can participate in the connectivity.

The dump file format

The dump file is a text file containing the ingredients of a LayoutToNetlist object:

• General information (database unit etc.)
• Layer definitions (what layers are there)
• Connectivity (what layer connect to which other layers)
• Global connections (what layers connect to which global net)
• Device abstracts (device cells with the terminal shapes)
• Circuits

Circuits are made from these components:

• Nets (electrical connections with the shapes making up the connections)
• Devices (the devices and what nets connect to their terminals)
• Pin (the connections the circuit makes to the outside)
• Subcircuits (other circuits being embedded into this circuit)

The information kept inside the dump file it's possible to derive the geometry of a net down to the device terminals.

This is a (shortened) sample of the dump file. The format is very likely to change, so don't take it too seriously:

# General section

top(RINGO)
unit(0.001)

# Layer section
# This section lists the mask layers (drawing or derived) and their connections.

# Mask layers
layer(poly)
layer(poly_lbl)
layer(diff_cont)
layer(poly_cont)
layer(metal1)
layer(metal1_lbl)
layer(via1)
layer(metal2)
layer(metal2_lbl)
layer(psd)
layer(nsd)

# Mask layer connectivity
connect(poly poly poly_lbl poly_cont)
connect(poly_lbl poly)
connect(diff_cont diff_cont metal1 psd nsd)
connect(poly_cont poly poly_cont metal1)
connect(metal1 diff_cont poly_cont metal1 metal1_lbl via1)
connect(metal1_lbl metal1)
connect(via1 metal1 via1 metal2)
connect(metal2 via1 metal2 metal2_lbl)
connect(metal2_lbl metal2)
connect(psd diff_cont psd)
connect(nsd diff_cont nsd)

# Device abstracts section
# Device abstracts list the pin shapes of the devices.
device(D$PMOS PMOS
 terminal(S
  rect(psd -650 -475 -125 475)
 )
 terminal(G
  rect(poly -125 -475 125 475)
 )
 terminal(D
  rect(psd 125 -475 675 475)
 )
)
device(D$PMOS$1 PMOS ...)
device(D$NMOS NMOS ...)
device(D$NMOS$1 NMOS ...)

# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(INV2

 # Nets with their geometries
 net(OUT
  rect(diff_cont 690 2890 910 3110)
  rect(diff_cont 690 2490 910 2710)
  rect(diff_cont 690 90 910 310)
  rect(diff_cont 690 -310 910 -90)
  polygon(metal1 800 20 800 380 940 380 940 1620 620 1620 620 2420 980 2420 980 1980 1300 1980 1300 20)
  rect(metal1 620 2420 980 3180)
  rect(metal1 620 -380 980 380)
  rect(metal1_lbl 799 1799 801 1801)
  rect(psd 525 2325 1050 3275)
  rect(nsd 525 -475 1050 475)
 )
 net(IN ... )
 net($2 ... )
 net($4 ... )
 net($5 ... )

 # Outgoing pins and their connections to nets
 pin(IN IN)
 pin($1 $2)
 pin(OUT OUT)
 pin($3 $4)
 pin($4 $5)

 # Devices and their connections
 device($1 D$PMOS
  location(-400 2800)
  param(L 0.25)
  param(W 0.95)
  param(AS 0.49875)
  param(AD 0.26125)
  terminal(S $2)
  terminal(G IN)
  terminal(D $5)
 )
 device($2 D$PMOS$1 ... )
 device($3 D$NMOS ... )
 device($4 D$NMOS$1 ... )

)
circuit(RINGO

 # Nets with their geometries
 net(FB ... )
 net(OSC ... )
 net(VSS ... )
 net(VDD ... )
 net($I19 ... )
 net($I8 ... )
 net($I7 ... )
 net($I6 ... )
 net($I5 ... )
 net($I4 ... )
 net($I3 ... )
 net($I2 ... )
 net($I1 ... )

 # Outgoing pins and their connections to nets
 pin(FB FB)
 pin(OSC OSC)
 pin(VSS VSS)
 pin(VDD VDD)

 # Subcircuits and their connections
 circuit($1 INV2 location(23760 0)
  pin(IN $I8)
  pin($1 FB)
  pin(OUT OSC)
  pin($3 VSS)
  pin($4 VDD)
 )
 circuit($2 INV2 location(0 0) ... )
 circuit($3 INV2 location(2640 0) ... )
 circuit($4 INV2 location(5280 0) ... )
 circuit($5 INV2 location(7920 0) ... )
 circuit($6 INV2 location(10560 0) ... )
 circuit($7 INV2 location(13200 0) ... )
 circuit($8 INV2 location(15840 0) ... )
 circuit($9 INV2 location(18480 0) ... )
 circuit($10 INV2 location(21120 0) ... )

)