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small bugs solved to make it compile
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coverage zfa section commented to make it compile (shall be finished in the future)
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Alfonso Carballo Boullosa committed Feb 13, 2024
1 parent b534184 commit c10a3cf
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Showing 5 changed files with 128 additions and 113 deletions.
12 changes: 6 additions & 6 deletions src/isa/riscv_zfa_instr.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,6 @@
class riscv_zfa_instr extends riscv_instr;
bit has_rm = 1'b0;
rand f_rounding_mode_t rm;
static riscv_instr_name_t rs2_cte_instr_name[$];

`uvm_object_utils(riscv_zfa_instr)

Expand All @@ -38,6 +37,7 @@ class riscv_zfa_instr extends riscv_instr;
has_imm = 1'b0;
end
end

I_FORMAT: begin
if (instr_name inside {FROUND_H, FROUNDNX_H, FROUND_S, FROUNDNX_S,
FROUND_D, FROUNDNX_D, FROUND_Q, FROUNDNX_Q}) begin
Expand Down Expand Up @@ -67,7 +67,7 @@ class riscv_zfa_instr extends riscv_instr;
end
super.pre_randomize();
endfunction

virtual function string convert2asm(string prefix = "");
string asm_str_final;
string asm_str;
Expand All @@ -77,10 +77,10 @@ class riscv_zfa_instr extends riscv_instr;
case (format)
I_FORMAT : begin // instr rd rs1
asm_str_final = $sformatf("%0s%0s, %0s, %0s", asm_str, rd.name(), rs1.name());
end
end
R_FORMAT : begin // instr rd rs1
asm_str_final = $sformatf("%0s%0s, %0s, %0s", asm_str, rd.name(), rs1.name(), rs2.name());
end
end

default: `uvm_info(`gfn, $sformatf("Unsupported format %0s", format.name()), UVM_LOW)
endcase
Expand All @@ -107,7 +107,7 @@ class riscv_zfa_instr extends riscv_instr;
FMVH_X_Q: get_opcode = 7'b1010011;
FMVP_Q_X: get_opcode = 7'b1010011;
FLEQ_H, FLTQ_H, FLEQ_S, FLTQ_S, FLEQ_D, FLTQ_D, FLEQ_Q, FLTQ_Q: get_opcode = 7'b1010011;
default : get_opcode = super.get_opcode();
default : get_opcode = super.get_opcode();
endcase
endfunction : get_opcode

Expand Down Expand Up @@ -159,7 +159,7 @@ class riscv_zfa_instr extends riscv_instr;
FCVTMOD_W_D : get_rs2_cte = 5'b01000;
FMVH_X_D : get_rs2_cte = 5'b00001;
FMVH_X_Q : get_rs2_cte = 5'b00001;
default : get_rs2_cte = 5'b0000;
default : get_rs2_cte = 5'b0000;
endcase
endfunction : get_rs2_cte

Expand Down
64 changes: 32 additions & 32 deletions src/isa/rv32zfa_instr.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*DEFINE_ZFA_INSTR
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
Expand All @@ -16,37 +16,37 @@
*/

// encoded as fmv instructions
`DEFINE_ZFA_INSTR(FLI_H, I_FORMAT, ARITHMETIC, RV32ZFA)
`DEFINE_ZFA_INSTR(FLI_S, I_FORMAT, ARITHMETIC, RV32ZFA)
`DEFINE_ZFA_INSTR(FLI_D, I_FORMAT, ARITHMETIC, RV32ZFA)
`DEFINE_ZFA_INSTR(FLI_Q, I_FORMAT, ARITHMETIC, RV32ZFA)
`DEFINE_ZFA_INSTR(FLI_H, I_FORMAT, ARITHMETIC, RV32ZFA);
`DEFINE_ZFA_INSTR(FLI_S, I_FORMAT, ARITHMETIC, RV32ZFA);
`DEFINE_ZFA_INSTR(FLI_D, I_FORMAT, ARITHMETIC, RV32ZFA);
`DEFINE_ZFA_INSTR(FLI_Q, I_FORMAT, ARITHMETIC, RV32ZFA);
// encoded as fmin/fmax instructions
`DEFINE_ZFA_INSTR(FMINM_H, R_FORMAT, ARITHMETIC, RV32ZFA)
`DEFINE_ZFA_INSTR(FMINM_S, R_FORMAT, ARITHMETIC, RV32ZFA)
`DEFINE_ZFA_INSTR(FMINM_D, R_FORMAT, ARITHMETIC, RV32ZFA)
`DEFINE_ZFA_INSTR(FMINM_Q, R_FORMAT, ARITHMETIC, RV32ZFA)
`DEFINE_ZFA_INSTR(FMAXM_H, R_FORMAT, ARITHMETIC, RV32ZFA)
`DEFINE_ZFA_INSTR(FMAXM_S, R_FORMAT, ARITHMETIC, RV32ZFA)
`DEFINE_ZFA_INSTR(FMAXM_D, R_FORMAT, ARITHMETIC, RV32ZFA)
`DEFINE_ZFA_INSTR(FMAXM_Q, R_FORMAT, ARITHMETIC, RV32ZFA)
`DEFINE_ZFA_INSTR(FMINM_H, R_FORMAT, ARITHMETIC, RV32ZFA);
`DEFINE_ZFA_INSTR(FMINM_S, R_FORMAT, ARITHMETIC, RV32ZFA);
`DEFINE_ZFA_INSTR(FMINM_D, R_FORMAT, ARITHMETIC, RV32ZFA);
`DEFINE_ZFA_INSTR(FMINM_Q, R_FORMAT, ARITHMETIC, RV32ZFA);
`DEFINE_ZFA_INSTR(FMAXM_H, R_FORMAT, ARITHMETIC, RV32ZFA);
`DEFINE_ZFA_INSTR(FMAXM_S, R_FORMAT, ARITHMETIC, RV32ZFA);
`DEFINE_ZFA_INSTR(FMAXM_D, R_FORMAT, ARITHMETIC, RV32ZFA);
`DEFINE_ZFA_INSTR(FMAXM_Q, R_FORMAT, ARITHMETIC, RV32ZFA);
// encoded as fcvt
`DEFINE_ZFA_INSTR(FROUND_H, I_FORMAT, ARITHMETIC, RV32ZFA)
`DEFINE_ZFA_INSTR(FROUNDNX_H, I_FORMAT, ARITHMETIC, RV32ZFA)
`DEFINE_ZFA_INSTR(FROUND_S, I_FORMAT, ARITHMETIC, RV32ZFA)
`DEFINE_ZFA_INSTR(FROUNDNX_S, I_FORMAT, ARITHMETIC, RV32ZFA)
`DEFINE_ZFA_INSTR(FROUND_D, I_FORMAT, ARITHMETIC, RV32ZFA)
`DEFINE_ZFA_INSTR(FROUNDNX_D, I_FORMAT, ARITHMETIC, RV32ZFA)
`DEFINE_ZFA_INSTR(FROUND_Q, I_FORMAT, ARITHMETIC, RV32ZFA)
`DEFINE_ZFA_INSTR(FROUNDNX_Q, I_FORMAT, ARITHMETIC, RV32ZFA)
`DEFINE_ZFA_INSTR(FCVTMOD_W_D, I_FORMAT, ARITHMETIC, RV32ZFA)
`DEFINE_ZFA_INSTR(FMVH_X_D, I_FORMAT, ARITHMETIC, RV32ZFA)
`DEFINE_ZFA_INSTR(FMVP_D_X, R_FORMAT, ARITHMETIC, RV32ZFA)
`DEFINE_ZFA_INSTR(FROUND_H, I_FORMAT, ARITHMETIC, RV32ZFA);
`DEFINE_ZFA_INSTR(FROUNDNX_H, I_FORMAT, ARITHMETIC, RV32ZFA);
`DEFINE_ZFA_INSTR(FROUND_S, I_FORMAT, ARITHMETIC, RV32ZFA);
`DEFINE_ZFA_INSTR(FROUNDNX_S, I_FORMAT, ARITHMETIC, RV32ZFA);
`DEFINE_ZFA_INSTR(FROUND_D, I_FORMAT, ARITHMETIC, RV32ZFA);
`DEFINE_ZFA_INSTR(FROUNDNX_D, I_FORMAT, ARITHMETIC, RV32ZFA);
`DEFINE_ZFA_INSTR(FROUND_Q, I_FORMAT, ARITHMETIC, RV32ZFA);
`DEFINE_ZFA_INSTR(FROUNDNX_Q, I_FORMAT, ARITHMETIC, RV32ZFA);
`DEFINE_ZFA_INSTR(FCVTMOD_W_D, I_FORMAT, ARITHMETIC, RV32ZFA);
`DEFINE_ZFA_INSTR(FMVH_X_D, I_FORMAT, ARITHMETIC, RV32ZFA);
`DEFINE_ZFA_INSTR(FMVP_D_X, R_FORMAT, ARITHMETIC, RV32ZFA);
// encoded as flt/fle...
`DEFINE_ZFA_INSTR(FLEQ_H, R_FORMAT, COMPARE, RV32ZFA)
`DEFINE_ZFA_INSTR(FLTQ_H, R_FORMAT, COMPARE, RV32ZFA)
`DEFINE_ZFA_INSTR(FLEQ_S, R_FORMAT, COMPARE, RV32ZFA)
`DEFINE_ZFA_INSTR(FLTQ_S, R_FORMAT, COMPARE, RV32ZFA)
`DEFINE_ZFA_INSTR(FLEQ_D, R_FORMAT, COMPARE, RV32ZFA)
`DEFINE_ZFA_INSTR(FLTQ_D, R_FORMAT, COMPARE, RV32ZFA)
`DEFINE_ZFA_INSTR(FLEQ_Q, R_FORMAT, COMPARE, RV32ZFA)
`DEFINE_ZFA_INSTR(FLTQ_Q, R_FORMAT, COMPARE, RV32ZFA)
`DEFINE_ZFA_INSTR(FLEQ_H, R_FORMAT, COMPARE, RV32ZFA);
`DEFINE_ZFA_INSTR(FLTQ_H, R_FORMAT, COMPARE, RV32ZFA);
`DEFINE_ZFA_INSTR(FLEQ_S, R_FORMAT, COMPARE, RV32ZFA);
`DEFINE_ZFA_INSTR(FLTQ_S, R_FORMAT, COMPARE, RV32ZFA);
`DEFINE_ZFA_INSTR(FLEQ_D, R_FORMAT, COMPARE, RV32ZFA);
`DEFINE_ZFA_INSTR(FLTQ_D, R_FORMAT, COMPARE, RV32ZFA);
`DEFINE_ZFA_INSTR(FLEQ_Q, R_FORMAT, COMPARE, RV32ZFA);
`DEFINE_ZFA_INSTR(FLTQ_Q, R_FORMAT, COMPARE, RV32ZFA);
4 changes: 2 additions & 2 deletions src/isa/rv64zfa_instr.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -15,5 +15,5 @@
* limitations under the License.
*/

`DEFINE_ZFA_INSTR(FMVH_X_Q, I_FORMAT, ARITHMETIC, RV64ZFA)
`DEFINE_ZFA_INSTR(FMVP_Q_X, R_FORMAT, ARITHMETIC, RV64ZFA)
`DEFINE_ZFA_INSTR(FMVH_X_Q, I_FORMAT, ARITHMETIC, RV64ZFA);
`DEFINE_ZFA_INSTR(FMVP_Q_X, R_FORMAT, ARITHMETIC, RV64ZFA);
159 changes: 86 additions & 73 deletions src/riscv_instr_cover_group.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -1127,6 +1127,19 @@ class riscv_instr_cover_group;
`FCLASS_INSTR_CG_BEGIN(fclass_h, H)
`CG_END

// // ZFA ext
// `FP_I2F_INSTR_CG_BEGIN(fli_h, H)
// `CG_END

// `FP_I2F_INSTR_CG_BEGIN(fli_s)
// `CG_END

// `FP_I2F_INSTR_CG_BEGIN(fli_d, D)
// `CG_END

// `FP_I2F_INSTR_CG_BEGIN(fli_q, Q)
// `CG_END

// B extension instructions ratified in v.1.00 (Zba, Zbb, Zbc, Zbs).
`ZBA_R_INSTR_CG_BEGIN(sh1add)
`CG_END
Expand Down Expand Up @@ -2338,44 +2351,44 @@ class riscv_instr_cover_group;
fmv_h_x_cg = new();
`CG_SELECTOR_END

`CG_SELECTOR_BEGIN(RV32ZFA)
fli_h_cg = new();
fli_s_cg = new();
fli_d_cg = new();
fli_q_cg = new();
fminm_h_cg = new();
fminm_s_cg = new();
fminm_d_cg = new();
fminm_q_cg = new();
fmaxm_h_cg = new();
fmaxm_s_cg = new();
fmaxm_d_cg = new();
fmaxm_q_cg = new();
fround_h_cg = new();
froundnx_h_cg = new();
fround_s_cg = new();
froundnx_s_cg = new();
fround_d_cg = new();
froundnx_d_cg = new();
fround_q_cg = new();
froundnx_q_cg = new();
fcvtmod_w_d_cg = new();
fmvh_x_d_cg = new();
fmvh_d_x_cg = new();
fleq_h_cg = new();
fltq_h_cg = new();
fleq_s_cg = new();
fltq_s_cg = new();
fleq_d_cg = new();
fltq_d_cg = new();
fleq_q_cg = new();
fltq_q_cg = new();
`CG_SELECTOR_END

`CG_SELECTOR_BEGIN(RV64ZFA)
fmvh_x_q_cg = new();
fmvh_q_x_cg = new();
`CG_SELECTOR_END
// `CG_SELECTOR_BEGIN(RV32ZFA)
// fli_h_cg = new();
// fli_s_cg = new();
// fli_d_cg = new();
// fli_q_cg = new();
// fminm_h_cg = new();
// fminm_s_cg = new();
// fminm_d_cg = new();
// fminm_q_cg = new();
// fmaxm_h_cg = new();
// fmaxm_s_cg = new();
// fmaxm_d_cg = new();
// fmaxm_q_cg = new();
// fround_h_cg = new();
// froundnx_h_cg = new();
// fround_s_cg = new();
// froundnx_s_cg = new();
// fround_d_cg = new();
// froundnx_d_cg = new();
// fround_q_cg = new();
// froundnx_q_cg = new();
// fcvtmod_w_d_cg = new();
// fmvh_x_d_cg = new();
// fmvh_d_x_cg = new();
// fleq_h_cg = new();
// fltq_h_cg = new();
// fleq_s_cg = new();
// fltq_s_cg = new();
// fleq_d_cg = new();
// fltq_d_cg = new();
// fleq_q_cg = new();
// fltq_q_cg = new();
// `CG_SELECTOR_END

// `CG_SELECTOR_BEGIN(RV64ZFA)
// fmvh_x_q_cg = new();
// fmvh_q_x_cg = new();
// `CG_SELECTOR_END

`CG_SELECTOR_BEGIN(RV64F)
fcvt_l_s_cg = new();
Expand Down Expand Up @@ -2769,40 +2782,40 @@ class riscv_instr_cover_group;
FLE_D : `SAMPLE_F(fle_d_cg, instr)
FCLASS_S : `SAMPLE_F(fclass_s_cg, instr)
FCLASS_D : `SAMPLE_F(fclass_d_cg, instr)
// RV ZFA
FLI_H : `SAMPLE_ZFA(fli_h_cg, instr)
FLI_S : `SAMPLE_ZFA(fli_s_cg, instr)
FLI_D : `SAMPLE_ZFA(fli_d_cg, instr)
FLI_Q : `SAMPLE_ZFA(fli_q_cg, instr)
FMINM_H : `SAMPLE_ZFA(fminm_h_cg, instr)
FMINM_S : `SAMPLE_ZFA(fminm_s_cg, instr)
FMINM_D : `SAMPLE_ZFA(fminm_d_cg, instr)
FMINM_Q : `SAMPLE_ZFA(fminm_q_cg, instr)
FMAXM_H : `SAMPLE_ZFA(fmaxm_h_cg, instr)
FMAXM_S : `SAMPLE_ZFA(fmaxm_s_cg, instr)
FMAXM_D : `SAMPLE_ZFA(fmaxm_d_cg, instr)
FMAXM_Q : `SAMPLE_ZFA(fmaxm_q_cg, instr)
FROUND_H : `SAMPLE_ZFA(fround_h_cg, instr)
FROUNDNX_H : `SAMPLE_ZFA(froundnx_h_cg, instr)
FROUND_S : `SAMPLE_ZFA(fround_s_cg, instr)
FROUNDNX_S : `SAMPLE_ZFA(froundnx_s_cg, instr)
FROUND_D : `SAMPLE_ZFA(fround_d_cg, instr)
FROUNDNX_D : `SAMPLE_ZFA(froundnx_d_cg, instr)
FROUND_Q : `SAMPLE_ZFA(fround_q_cg, instr)
FROUNDNX_Q : `SAMPLE_ZFA(froundnx_q_cg, instr)
FCVTMOD_W_D : `SAMPLE_ZFA(fcvtmod_w_d_cg, instr)
FMVH_X_D : `SAMPLE_ZFA(fmvh_x_d_cg, instr)
FMVP_D_X : `SAMPLE_ZFA(fmvh_d_x_cg, instr)
FLEQ_H : `SAMPLE_ZFA(fleq_h_cg, instr)
FLTQ_H : `SAMPLE_ZFA(fltq_h_cg, instr)
FLEQ_S : `SAMPLE_ZFA(fleq_s_cg, instr)
FLTQ_S : `SAMPLE_ZFA(fltq_s_cg, instr)
FLEQ_D : `SAMPLE_ZFA(fleq_d_cg, instr)
FLTQ_D : `SAMPLE_ZFA(fltq_d_cg, instr)
FLEQ_Q : `SAMPLE_ZFA(fleq_q_cg, instr)
FLTQ_Q : `SAMPLE_ZFA(fltq_q_cg, instr)
FMVH_X_Q : `SAMPLE_ZFA(fmvh_x_q_cg, instr)
FMVP_Q_X : `SAMPLE_ZFA(fmvh_q_x_cg, instr)
// // RV ZFA
// FLI_H : `SAMPLE_ZFA(fli_h_cg, instr)
// FLI_S : `SAMPLE_ZFA(fli_s_cg, instr)
// FLI_D : `SAMPLE_ZFA(fli_d_cg, instr)
// FLI_Q : `SAMPLE_ZFA(fli_q_cg, instr)
// FMINM_H : `SAMPLE_ZFA(fminm_h_cg, instr)
// FMINM_S : `SAMPLE_ZFA(fminm_s_cg, instr)
// FMINM_D : `SAMPLE_ZFA(fminm_d_cg, instr)
// FMINM_Q : `SAMPLE_ZFA(fminm_q_cg, instr)
// FMAXM_H : `SAMPLE_ZFA(fmaxm_h_cg, instr)
// FMAXM_S : `SAMPLE_ZFA(fmaxm_s_cg, instr)
// FMAXM_D : `SAMPLE_ZFA(fmaxm_d_cg, instr)
// FMAXM_Q : `SAMPLE_ZFA(fmaxm_q_cg, instr)
// FROUND_H : `SAMPLE_ZFA(fround_h_cg, instr)
// FROUNDNX_H : `SAMPLE_ZFA(froundnx_h_cg, instr)
// FROUND_S : `SAMPLE_ZFA(fround_s_cg, instr)
// FROUNDNX_S : `SAMPLE_ZFA(froundnx_s_cg, instr)
// FROUND_D : `SAMPLE_ZFA(fround_d_cg, instr)
// FROUNDNX_D : `SAMPLE_ZFA(froundnx_d_cg, instr)
// FROUND_Q : `SAMPLE_ZFA(fround_q_cg, instr)
// FROUNDNX_Q : `SAMPLE_ZFA(froundnx_q_cg, instr)
// FCVTMOD_W_D : `SAMPLE_ZFA(fcvtmod_w_d_cg, instr)
// FMVH_X_D : `SAMPLE_ZFA(fmvh_x_d_cg, instr)
// FMVP_D_X : `SAMPLE_ZFA(fmvh_d_x_cg, instr)
// FLEQ_H : `SAMPLE_ZFA(fleq_h_cg, instr)
// FLTQ_H : `SAMPLE_ZFA(fltq_h_cg, instr)
// FLEQ_S : `SAMPLE_ZFA(fleq_s_cg, instr)
// FLTQ_S : `SAMPLE_ZFA(fltq_s_cg, instr)
// FLEQ_D : `SAMPLE_ZFA(fleq_d_cg, instr)
// FLTQ_D : `SAMPLE_ZFA(fltq_d_cg, instr)
// FLEQ_Q : `SAMPLE_ZFA(fleq_q_cg, instr)
// FLTQ_Q : `SAMPLE_ZFA(fltq_q_cg, instr)
// FMVH_X_Q : `SAMPLE_ZFA(fmvh_x_q_cg, instr)
// FMVP_Q_X : `SAMPLE_ZFA(fmvh_q_x_cg, instr)
// RV half-precission
FLH : `SAMPLE_ZFH(flh_cg, instr)
FSH : `SAMPLE_ZFH(fsh_cg, instr)
Expand Down Expand Up @@ -3053,7 +3066,7 @@ class riscv_instr_cover_group;
RV32ZBA, RV32ZBB, RV32ZBC, RV32ZBS,
RV64ZBA, RV64ZBB, RV64ZBC, RV64ZBS,
RV32ZBKB, RV64ZBKB, RV32ZBKC, RV32ZBKX,
RV32ZFA, RV64ZFA,
// RV32ZFA, RV64ZFA,
RV32ZCB, RV64ZCB, RV32ZFH, RV64ZFH})) begin
if (((instr_name inside {URET}) && !support_umode_trap) ||
((instr_name inside {SRET, SFENCE_VMA}) &&
Expand Down
2 changes: 2 additions & 0 deletions src/riscv_instr_pkg.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1698,6 +1698,7 @@ package riscv_instr_pkg;
typedef class riscv_zbkx_instr;
typedef class riscv_zbs_instr;
typedef class riscv_zbkb_instr;
typedef class riscv_zfa_instr;
typedef class riscv_zcb_instr;
typedef class riscv_b_instr;
`include "riscv_instr_gen_config.sv"
Expand Down Expand Up @@ -1737,6 +1738,7 @@ package riscv_instr_pkg;
`include "isa/rv64zcb_instr.sv"
`include "isa/rv32zfh_instr.sv"
`include "isa/rv64zfh_instr.sv"
`include "isa/riscv_zfa_instr.sv"
`include "isa/rv32zfa_instr.sv"
`include "isa/rv64zfa_instr.sv"

Expand Down

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