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Fork updated from chipsalliance/riscv-dv #1

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Fork updated from chipsalliance/riscv-dv

Fork updated from chipsalliance/riscv-dv #1

Run time

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Job Run time
generate-config
3s
generate-config
3s
build-spike / Build Spike
7m 13s
build-spike / Build Spike
7m 13s
generate-code (riscv_arithmetic_basic_test, uvm)
1s
generate-code (riscv_arithmetic_basic_test, uvm)
1s
generate-code (riscv_rand_instr_test, uvm)
1s
generate-code (riscv_rand_instr_test, uvm)
1s
generate-code (riscv_jump_stress_test, uvm)
1s
generate-code (riscv_jump_stress_test, uvm)
1s
generate-code (riscv_loop_test, uvm)
1s
generate-code (riscv_loop_test, uvm)
1s
generate-code (riscv_rand_jump_test, uvm)
1s
generate-code (riscv_rand_jump_test, uvm)
1s
generate-code (riscv_mmu_stress_test, uvm)
1s
generate-code (riscv_mmu_stress_test, uvm)
1s
generate-code (riscv_no_fence_test, uvm)
1s
generate-code (riscv_no_fence_test, uvm)
1s
generate-code (riscv_illegal_instr_test, uvm)
1s
generate-code (riscv_illegal_instr_test, uvm)
1s
generate-code (riscv_ebreak_test, uvm)
1s
generate-code (riscv_ebreak_test, uvm)
1s
generate-code (riscv_ebreak_debug_mode_test, uvm)
1s
generate-code (riscv_ebreak_debug_mode_test, uvm)
1s
generate-code (riscv_full_interrupt_test, uvm)
1s
generate-code (riscv_full_interrupt_test, uvm)
1s
generate-code (riscv_unaligned_load_store_test, uvm)
1s
generate-code (riscv_unaligned_load_store_test, uvm)
1s
generate-code (riscv_non_compressed_instr_test, uvm)
1s
generate-code (riscv_non_compressed_instr_test, uvm)
1s
generate-code (riscv_hint_instr_test, uvm)
1s
generate-code (riscv_hint_instr_test, uvm)
1s
generate-code (riscv_pmp_test, uvm)
1s
generate-code (riscv_pmp_test, uvm)
1s
generate-code (riscv_arithmetic_basic_test, pyflow)
1s
generate-code (riscv_arithmetic_basic_test, pyflow)
1s
run-tests
0s
run-tests
0s
15m 4s