Upload psoc6pdl 1.5.2.3446

RELEASE.md

@@ -1,28 +1,34 @@
-# PSoC 6 Peripheral Driver Library v1.5.1
+# PSoC 6 Peripheral Driver Library v1.5.2
 
-Please refer to the [README.md](./README.md) and the [PDL API Reference Manual](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/index.html) for a complete description of the Peripheral Driver Library.
+Please refer to the [README.md](./README.md) and the
+[PDL API Reference Manual](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/index.html)
+for a complete description of the Peripheral Driver Library.
 
-### New Features
+## New Features
 
-* New ECO calculation algorithm
+* No new features
 
-### Updated Personalities
+## Updated Personalities
 
-* ECO 2.0 - added new parameter C0; narrowed the frequency range to 16..35 MHz; updated the calculation algorithm per ECO Trimming section of the device TRM.
+* WiFi - Fix build warning in the generated code. Minor parameter name updates.
 
-### Updated Drivers
+## Updated Drivers
 
-* [SysClk 2.0](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sysclk.html)
+* [SD Host 1.50](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sd__host.html)
+* [CTB 1.10.2](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__ctb.html)
+* [SysLib 2.50.3](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syslib.html)
 
-### Known Issues
+## Known Issues
 
-None
+See the Known Issues section of
+[SysLib](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syslib.html)
+driver.
 
-### Defect Fixes
+## Defect Fixes
 
 See the Changelog section of each Driver in the [PDL API Reference](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/modules.html) for all fixes and updates.
 
-### Supported Software and Tools
+## Supported Software and Tools
 
 This version of PDL was validated for compatibility with the following Software and Tools:
 
@@ -36,7 +42,7 @@ This version of PDL was validated for compatibility with the following Software
 | ARM Compiler 6                                                                | 6.13         |
 | FreeRTOS                                                                      | 10.0.1       |
 
-### More information
+## More information
 
 * [Peripheral Driver Library README.md](./README.md)
 * [Peripheral Driver Library API Reference Manual](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/index.html)
@@ -46,6 +52,6 @@ This version of PDL was validated for compatibility with the following Software
 * [PSoC 6 Technical Reference Manuals](https://www.cypress.com/search/all/PSoC%206%20Technical%20Reference%20Manual?f%5b0%5d=meta_type%3Atechnical_documents&f%5b1%5d=resource_meta_type%3A583)
 * [PSoC 6 MCU Datasheets](https://www.cypress.com/search/all?f%5b0%5d=meta_type%3Atechnical_documents&f%5b1%5d=resource_meta_type%3A575&f%5b2%5d=field_related_products%3A114026)
 * [Cypress Semiconductor](http://www.cypress.com)
-  
+
 ---
 © Cypress Semiconductor Corporation, 2020.

docs/pdl_api_reference_manual/html/group__group__ctb.html

@@ -235,6 +235,8 @@ <h1><a class="anchor" id="group_ctb_changelog"></a>
 <tr>
 <th>Version</th><th>Changes</th><th>Reason for Change </th></tr>
 <tr>
+<td>1.10.2 </td><td>The <a class="el" href="group__group__ctb__functions__init.html#ga11187bf8d766321decd675d3f666adb1">Cy_CTB_Init</a> function description is expanded with a clarification note. </td><td>Documentation enhancement based on a usability feedback.  </td></tr>
+<tr>
 <td>1.10.1 </td><td>Added header guard CY_IP_MXS40PASS to the source file. </td><td>To enable the PDL compilation with wounded out IP blocks.  </td></tr>
 <tr>
 <td rowspan="2">1.10 </td><td>Flattened the organization of the driver source code into the single source directory and the single include directory.  </td><td>Driver library directory-structure simplification.   </td></tr>

docs/pdl_api_reference_manual/html/group__group__ctb__functions__init.html

@@ -139,6 +139,7 @@ <h2 class="memtitle"><span class="permalink"><a href="#ga11187bf8d766321decd675d
 
 <p>Initialize or restore the CTB and both opamps according to the provided settings. </p>
 <p>Parameters are usually set only once, at initialization.</p>
+<dl class="section note"><dt>Note</dt><dd>This function call disables a whole CTB block, call <a class="el" href="group__group__ctb__functions__init.html#gac80e1468e965c0ab15c3b14c15bb6c3d">Cy_CTB_Enable</a> after this function call.</dd></dl>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
     <tr><td class="paramname">base</td><td>Pointer to structure describing registers</td></tr>

docs/pdl_api_reference_manual/html/group__group__sd__host.html

@@ -201,7 +201,9 @@ <h1><a class="anchor" id="group_sd_host_Changelog"></a>
 <tr>
 <th>Version</th><th>Changes</th><th>Reason for Change </th></tr>
 <tr>
-<td>1.40 </td><td>Added a possibility to customize the SD clock rump up time during wakeup from deep sleep, see <a class="el" href="group__group__sd__host__low__level__functions.html#ga06ae777b53c8bcc0eeab12a7302af3be">Cy_SD_Host_DeepSleepCallback</a> description for details. </td><td>Workaround for cases of specific wakeup timing requirements.  </td></tr>
+<td>1.50 </td><td>The default value of the SD-clock rump-up time during a wakeup from Deep Sleep is reduced to 1 us, for details, see <a class="el" href="group__group__sd__host__low__level__functions.html#ga06ae777b53c8bcc0eeab12a7302af3be">Cy_SD_Host_DeepSleepCallback</a> description. </td><td>Optimization for cases of specific wakeup timing requirements.  </td></tr>
+<tr>
+<td>1.40 </td><td>Added a possibility to customize the SD-clock rump-up time during a wakeup from Deep Sleep, for details, see <a class="el" href="group__group__sd__host__low__level__functions.html#ga06ae777b53c8bcc0eeab12a7302af3be">Cy_SD_Host_DeepSleepCallback</a> description. </td><td>Workaround for cases of specific wakeup timing requirements.  </td></tr>
 <tr>
 <td>1.30 </td><td>The internal function implementation is changed. </td><td>Code efficiency enhancement, minor defect fixing.  </td></tr>
 <tr>

docs/pdl_api_reference_manual/html/group__group__sd__host__low__level__functions.html

@@ -1745,7 +1745,7 @@ <h2 class="memtitle"><span class="permalink"><a href="#ga06ae777b53c8bcc0eeab12a
 <p>This function handles the transition of the SD Host into and out of Deep Sleep mode. </p>
 <p>It disables SD CLK before going to Deep Sleep mode and enables SD CLK after wake up from Deep Sleep mode. If the DAT line is active, or a read (write) transfer is being executed on the bus, the device cannot enter Deep Sleep mode.</p>
 <p>This function must be called during execution of <a class="el" href="group__group__syspm__functions__power.html#ga5150c28fe4d2626720c1fbf74b3111ca">Cy_SysPm_CpuEnterDeepSleep</a>. To do it, register this function as a callback before calling <a class="el" href="group__group__syspm__functions__power.html#ga5150c28fe4d2626720c1fbf74b3111ca">Cy_SysPm_CpuEnterDeepSleep</a> : specify <a class="el" href="group__group__syspm__data__enumerates.html#gga8c2960c0164ead1cfa86e7d6846b6ff0abc51d74deff0ceea4304b01b2d57bd9d">CY_SYSPM_DEEPSLEEP</a> as the callback type and call <a class="el" href="group__group__syspm__functions__callback.html#ga0d58b00c8dc764a6371590f70e2f73c7">Cy_SysPm_RegisterCallback</a>.</p>
-<dl class="section note"><dt>Note</dt><dd>When waking up from Deep Sleep, the SD Host driver requires up to 100ms for clock stabilization. By default the SD Host driver will wait this length of time on power up. The waiting loop is implemented in this function. If the application is time sensitive this delay can be overridden by the application by defining <a class="el" href="group__group__sd__host__macros__general__purpose.html#gadd91111c5e80b2cc62f1adf75de3183c">CY_SD_HOST_CLK_RAMP_UP_TIME_MS_WAKEUP</a> to a lower value. This allows the application to perform other operations while the clock is stabilizing in the background. However, the application must still make sure that the SD Host clock has had time to stabilize before attempting to use the SD card. The recommended way to override the value is to specify this as a custom define on the compiler command line. This can be done by appending the entry to the DEFINES variable in the application Makefile. Eg: DEFINES+=CY_SD_HOST_CLK_RAMP_UP_TIME_MS_WAKEUP=40.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>When waking up from Deep Sleep, the SD Host driver requires up to 1 us for clock stabilization. By default the SD Host driver will wait this length of time on power up. The waiting loop is implemented in this function. If the application is time sensitive this delay can be overridden by the application by defining <a class="el" href="group__group__sd__host__macros__general__purpose.html#gae6b0b7d64c1290282c330f76b0ccb65d">CY_SD_HOST_CLK_RAMP_UP_TIME_US_WAKEUP</a>. This allows the application to perform other operations while the clock is stabilizing in the background. However, the application must still make sure that the SD Host clock has had time to stabilize before attempting to use the SD card. The recommended way to override the value is to specify this as a custom define on the compiler command line. This can be done by appending the entry to the DEFINES variable in the application Makefile. Eg: DEFINES+=CY_SD_HOST_CLK_RAMP_UP_TIME_US_WAKEUP=40.</dd></dl>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
     <tr><td class="paramname">callbackParams</td><td>The pointer to the callback parameters structure <a class="el" href="structcy__stc__syspm__callback__params__t.html">cy_stc_syspm_callback_params_t</a>.</td></tr>

docs/pdl_api_reference_manual/html/group__group__sd__host__macros__general__purpose.html

@@ -121,9 +121,9 @@
 <tr class="memitem:gaa56807ade05f5f8ff34fa71e8f1f8eb8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sd__host__macros__general__purpose.html#gaa56807ade05f5f8ff34fa71e8f1f8eb8">CY_SD_HOST_CLK_RAMP_UP_TIME_MS</a>&#160;&#160;&#160;(100UL)</td></tr>
 <tr class="memdesc:gaa56807ade05f5f8ff34fa71e8f1f8eb8"><td class="mdescLeft">&#160;</td><td class="mdescRight">The host power ramp up time.  <a href="#gaa56807ade05f5f8ff34fa71e8f1f8eb8">More...</a><br /></td></tr>
 <tr class="separator:gaa56807ade05f5f8ff34fa71e8f1f8eb8"><td class="memSeparator" colspan="2">&#160;</td></tr>
-<tr class="memitem:gadd91111c5e80b2cc62f1adf75de3183c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sd__host__macros__general__purpose.html#gadd91111c5e80b2cc62f1adf75de3183c">CY_SD_HOST_CLK_RAMP_UP_TIME_MS_WAKEUP</a>&#160;&#160;&#160;(<a class="el" href="group__group__sd__host__macros__general__purpose.html#gaa56807ade05f5f8ff34fa71e8f1f8eb8">CY_SD_HOST_CLK_RAMP_UP_TIME_MS</a>)</td></tr>
-<tr class="memdesc:gadd91111c5e80b2cc62f1adf75de3183c"><td class="mdescLeft">&#160;</td><td class="mdescRight">The host power ramp up time during wake up from deep sleep.  <a href="#gadd91111c5e80b2cc62f1adf75de3183c">More...</a><br /></td></tr>
-<tr class="separator:gadd91111c5e80b2cc62f1adf75de3183c"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gae6b0b7d64c1290282c330f76b0ccb65d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sd__host__macros__general__purpose.html#gae6b0b7d64c1290282c330f76b0ccb65d">CY_SD_HOST_CLK_RAMP_UP_TIME_US_WAKEUP</a>&#160;&#160;&#160;(1U)</td></tr>
+<tr class="memdesc:gae6b0b7d64c1290282c330f76b0ccb65d"><td class="mdescLeft">&#160;</td><td class="mdescRight">The default host power ramp up time during wake up from deep sleep.  <a href="#gae6b0b7d64c1290282c330f76b0ccb65d">More...</a><br /></td></tr>
+<tr class="separator:gae6b0b7d64c1290282c330f76b0ccb65d"><td class="memSeparator" colspan="2">&#160;</td></tr>
 <tr class="memitem:gaf84a4e57cec03657fee98b7643c23c19"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sd__host__macros__general__purpose.html#gaf84a4e57cec03657fee98b7643c23c19">CY_SD_HOST_ADMA_NOP</a>&#160;&#160;&#160;(0x0UL)</td></tr>
 <tr class="memdesc:gaf84a4e57cec03657fee98b7643c23c19"><td class="mdescLeft">&#160;</td><td class="mdescRight">Does not execute the current line and go to next line.  <a href="#gaf84a4e57cec03657fee98b7643c23c19">More...</a><br /></td></tr>
 <tr class="separator:gaf84a4e57cec03657fee98b7643c23c19"><td class="memSeparator" colspan="2">&#160;</td></tr>
@@ -245,19 +245,19 @@ <h2 class="memtitle"><span class="permalink"><a href="#gaa56807ade05f5f8ff34fa71
 
 </div>
 </div>
-<a id="gadd91111c5e80b2cc62f1adf75de3183c"></a>
-<h2 class="memtitle"><span class="permalink"><a href="#gadd91111c5e80b2cc62f1adf75de3183c">&#9670;&nbsp;</a></span>CY_SD_HOST_CLK_RAMP_UP_TIME_MS_WAKEUP</h2>
+<a id="gae6b0b7d64c1290282c330f76b0ccb65d"></a>
+<h2 class="memtitle"><span class="permalink"><a href="#gae6b0b7d64c1290282c330f76b0ccb65d">&#9670;&nbsp;</a></span>CY_SD_HOST_CLK_RAMP_UP_TIME_US_WAKEUP</h2>
 
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define CY_SD_HOST_CLK_RAMP_UP_TIME_MS_WAKEUP&#160;&#160;&#160;(<a class="el" href="group__group__sd__host__macros__general__purpose.html#gaa56807ade05f5f8ff34fa71e8f1f8eb8">CY_SD_HOST_CLK_RAMP_UP_TIME_MS</a>)</td>
+          <td class="memname">#define CY_SD_HOST_CLK_RAMP_UP_TIME_US_WAKEUP&#160;&#160;&#160;(1U)</td>
         </tr>
       </table>
 </div><div class="memdoc">
 
-<p>The host power ramp up time during wake up from deep sleep. </p>
+<p>The default host power ramp up time during wake up from deep sleep. </p>
 
 </div>
 </div>

docs/pdl_api_reference_manual/html/group__group__syslib.html

@@ -123,7 +123,7 @@ <h1><a class="anchor" id="group_syslib_configuration"></a>
 <td>CY_ASSERT_CLASS_3 </td><td>CY_ASSERT_L3 </td><td>A parameter that is an enum constant  </td></tr>
 </table>
 <p>Firmware defines which ASSERT class is enabled by defining CY_ASSERT_LEVEL. This is a compiler command line argument, similar to how the DEBUG / NDEBUG macro is passed. <br />
- Enabling any class also enables any lower-numbered class. CY_ASSERT_CLASS_3 is the default level, and it enables asserts for all three classes. The following example shows the command-line option to enable all the assert levels: </p><div class="fragment"><div class="line">-D <a class="code" href="group__group__syslib__macros__assert.html#gaac6d3358f192068b723bc4bb50a06967">CY_ASSERT_LEVEL</a>=<a class="code" href="group__group__syslib__macros__assert.html#ga519c4c299506f8a54e3a99e58a435f0a">CY_ASSERT_CLASS_3</a> </div></div><!-- fragment --> <dl class="section note"><dt>Note</dt><dd>The use of special characters, such as spaces, parenthesis, etc. must be protected with quotes.</dd></dl>
+Enabling any class also enables any lower-numbered class. CY_ASSERT_CLASS_3 is the default level, and it enables asserts for all three classes. The following example shows the command-line option to enable all the assert levels: </p><div class="fragment"><div class="line">-D <a class="code" href="group__group__syslib__macros__assert.html#gaac6d3358f192068b723bc4bb50a06967">CY_ASSERT_LEVEL</a>=<a class="code" href="group__group__syslib__macros__assert.html#ga519c4c299506f8a54e3a99e58a435f0a">CY_ASSERT_CLASS_3</a> </div></div><!-- fragment --> <dl class="section note"><dt>Note</dt><dd>The use of special characters, such as spaces, parenthesis, etc. must be protected with quotes.</dd></dl>
 <p>After CY_ASSERT_LEVEL is defined, firmware can use one of the three level macros to make an assertion. For example, if the parameter can vary between devices, firmware uses the L1 macro. </p><div class="fragment"><div class="line"><a class="code" href="group__group__syslib__macros__assert.html#gabb4e5c6e694fe418794cbd8f93301532">CY_ASSERT_L1</a>(clkPath &lt; SRSS_NUM_CLKPATH); </div></div><!-- fragment --><p> If the parameter has bounds, firmware uses L2. </p><div class="fragment"><div class="line"><a class="code" href="group__group__syslib__macros__assert.html#gae6c8c534d15ba72d74dc23b384a28bf0">CY_ASSERT_L2</a>(trim &lt;= CY_CTB_TRIM_VALUE_MAX); </div></div><!-- fragment --><p> If the parameter is an enum, firmware uses L3. </p><div class="fragment"><div class="line"><a class="code" href="group__group__syslib__macros__assert.html#gaea99c6824b32df70dbeb97d87d5410a1">CY_ASSERT_L3</a>(config-&gt;LossAction &lt;= CY_SYSCLK_CSV_ERROR_FAULT_RESET); </div></div><!-- fragment --><p> Each check uses the appropriate level macro for the kind of parameter being checked. If a particular assert class/level is not enabled, then the assert does nothing.</p>
 <h1><a class="anchor" id="group_syslib_more_information"></a>
 More Information</h1>
@@ -138,12 +138,22 @@ <h1><a class="anchor" id="group_syslib_MISRA"></a>
 <tr>
 <td>18.4 </td><td>R </td><td>Unions shall not be used. </td><td>The unions are used for CFSR, HFSR and SHCSR Fault Status Registers content access as a word in code and as a structure during debug.  </td></tr>
 </table>
+<h1><a class="anchor" id="group_syslib_errata"></a>
+Known Issues</h1>
+<table class="doxtable">
+<tr>
+<th>Issue</th><th>Workaround </th></tr>
+<tr>
+<td>The function malloc() does not return an error when the allocation size is bigger than the heap size.  </td><td>PDL does not implement the _sbrk function. The user needs to add custom _sbrk function.   </td></tr>
+</table>
 <h1><a class="anchor" id="group_syslib_changelog"></a>
 Changelog</h1>
 <table class="doxtable">
 <tr>
 <th>Version</th><th>Changes</th><th>Reason for Change </th></tr>
 <tr>
+<td>2.50.3 </td><td>Add section Known Issues </td><td>Documentation update and clarification.  </td></tr>
+<tr>
 <td>2.50.1 </td><td>Used the core library defines for the message codes forming. </td><td>Improve PDL code base.  </td></tr>
 <tr>
 <td>2.50 </td><td>Moved following macros to the core library: CY_LO8,CY_HI8,CY_LO16,CY_HI16,CY_SWAP_ENDIAN16,CY_SWAP_ENDIAN32, CY_SWAP_ENDIAN64,CY_GET_REG8,CY_SET_REG8,CY_GET_REG16,CY_SET_REG16, CY_GET_REG24,CY_SET_REG24,CY_GET_REG32,CY_SET_REG32,_CLR_SET_FLD32U, CY_REG32_CLR_SET,_CLR_SET_FLD16U,CY_REG16_CLR_SET,_CLR_SET_FLD8U, CY_REG8_CLR_SET,_BOOL2FLD,_FLD2BOOL,CY_SYSLIB_DIV_ROUND, CY_SYSLIB_DIV_ROUNDUP,CY_NOINIT,CY_SECTION,CY_UNUSED,CY_NOINLINE, CY_ALIGN,CY_RAMFUNC_BEGIN,CY_RAMFUNC_END. Use at least version 1.1 of the core library: <a href="https://github.com/cypresssemiconductorco/core-lib">https://github.com/cypresssemiconductorco/core-lib</a>. </td><td>Improve PDL code base.  </td></tr>