fix(misc): wrapper extmem wires, remove latch #857
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- Update mkregs.py to generate verilator testbench code - Add iob_tasks equivalent for verilator - Update iob-soc verilator testbench to use new functions and drive ethernet [WIP]
- update python scripts to generate extmem wires verilog snippet for mwrap.v module. This declares wires with number of external memory interfaces - minor python script fixes
Update `iob_native_t` of iob_tasks to support various data types.
The system seems to be stuck before printing any messages, and I cannot debug it because verilator is not generating initial traces. I´m not sure why. Verilator is only generating traces after about 1700000ns, but that time varies when re-running the simulation.
Move $dumpvars from sim_wrapper to verilog testbench. Turns out calling $dumpvars() from sim_wrapper was interfering with verilator testbench tfp->dump() calls, causing wrong trace data.
Previously could only read 1 byte from registers. Now it can read up to 4 bytes.
Pass `VTHREADS` variable to `make` command to enable multi-thread. Update iob_tasks.cpp to allow delayed start of VCD trace dump.
- add default value for `araddr_int` in `axis2axi_out.v` to stop some tools (ex. quartus) for inferring latches
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araddr_intinaxis2axi_out.vto stop some tools (ex. quartus) for inferring latches